Work Files Saved Searches
   My Account                                                  Search:   Quick/Number   Boolean   Advanced   Derwent    Help   


 The Delphion Integrated View

  Buy Now:   Buy PDF- 8pp  PDF  |   File History  |   Other choices   
  Tools:  Citation Link  |  Add to Work File:    
  View:  Expand Details   |  INPADOC   |  Jump to: 
  Go to:  Derwent  
 Email this to a friend  Email this to a friend 
       
Title: US4319357: Double error correction using single error correcting code
[ Derwent Title ]


Country: US United States of America

View Images High
Resolution

 Low
 Resolution

 
8 pages

 
Inventor: Bossen, Douglas C.; Poughkeepsie, NY

Assignee: International Business Machines Corp., Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
 News, Profiles, Stocks and More about this company

Published / Filed: 1982-03-09 / 1979-12-14

Application Number: US1979000103633

IPC Code: Advanced: G06F 11/10; G06F 12/16;
Core: more...
IPC-7: G06F 11/10;

ECLA Code: G06F11/10M2D3; S06F11/10M2D1D;

U.S. Class: Current: 714/753; 714/E11.049;
Original: 371/038;

Field of Search: 371/037,38 364/200,900

Priority Number:
1979-12-14  US1979000103633

Abstract:     A single error correcting double error detecting (SEC/DED) error correcting code for a memory is used to correct one fixed error and one transitory error in a data word stored in the memory. The erroneous data word and syndrome generated therefrom by the error correcting code circuitry are saved while the memory location of the flawed word is checked to determine the location of the one fixed error using a ancillatory error correction technique. A syndrome is then generated for the word assuming only a single fixed error in the location determined using the ancillatory technique. Thereafter, the generated and saved syndromes are exclusive OR'd together to obtain another syndrome locating the position of the transitory error. With both errors located, the word is corrected by inverting the erroneous data bits.

Attorney, Agent or Firm: Murray, James E. ;

Primary / Asst. Examiners: Atkinson, Charles E.;

INPADOC Legal Status: Show legal status actions          Buy Now: Family Legal Status Report

Family: Show 7 known family members

First Claim:
Show all 3 claims
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:     1. In an error correcting system for a memory using a ECC code capable of correcting a single error and detecting a double error, a method for correcting a word which has one fixed error and one transitory error comprising the steps of:
  • (a) saving the data and syndrome generated by the ECC code circuitry for said word;
  • (b) determining the location of said one hard error using an ancillary error location technique;
  • (c) generating a syndrome for said word assuming only a single error in the location determined by (b);
  • (d) exclusive ORing the syndrome generated by step (c) with the syndrome stored in step (a) to obtain the syndrome locating the position of the transitory error;
  • (e) correcting the transitory errror.


Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 25 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (25)   |   Backward references (6)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
  US3656107  1972-04 Hsiao et al.  International Business Machines Corporation AUTOMATIC DOUBLE ERROR DETECTION AND CORRECTION APPARATUS
Buy PDF- 12pp US4100403  1978-07 Eggenberger et al.  International Business Machines Corporation Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays
Buy PDF- 18pp US4139148  1979-02 Scheuneman et al.  Sperry Rand Corporation Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory
Buy PDF- 9pp US4163147  1979-07 Scheuneman et al.  Sperry Rand Corporation Double bit error correction using double bit complementing
Buy PDF- 8pp US4175692  1979-11 Watanabe  Hitachi, Ltd. Error correction and detection systems
Buy PDF- 11pp US4209846  1980-06 Seppa  Sperry Corporation Memory error logger which sorts transient errors from solid errors
       
Foreign References: None

Inquire Regarding Licensing

Powered by Verity


Plaques from Patent Awards      Gallery of Obscure PatentsNominate this for the Gallery...

Thomson Reuters Copyright © 1997-2010 Thomson Reuters 
Subscriptions  |  Web Seminars  |  Privacy  |  Terms & Conditions  |  Site Map  |  Contact Us  |  Help