 |
|
|
|
|
|
 Title: |
US5027270:
Processor controlled interface with instruction streaming
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Riordan, Thomas J.; Sunnyvale, CA
Ries, Paul S.; San Jose, CA
Hudson, Edwin L.; Santa Clara, CA
Killian, Earl A.; Palo Alto, CA
|
| Assignee: |
Mips Computer Systems, Inc., Sunnyvale, CA
other patents from MIPS COMPUTER SYSTEMS, INC. (378135) (approx. 17)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1991-06-25
/ 1988-10-11
|
| Application Number: |
US1988000255791
|
| IPC Code: |
Advanced:
G06F 9/38;
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/12;
G06F 13/00;
|
| U.S. Class: |
Current:
711/140;
711/125;
711/E12.051;
712/E09.055;
Original:
364/200;
364/243.4;
364/243.41;
|
| Field of Search: |
364/200 MS File,900 MS File
|
| Priority Number: |
| 1988-10-11 |
US1988000255791 |
|
| Abstract: |
A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.
|
| Attorney, Agent or Firm: |
Townsend and Townsend ;
|
| Primary / Asst. Examiners: |
Eng, David Y.;
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
| Family: |
Show 6 known family members
|
First Claim:
Show all 3 claims |
What is claimed is:
1. In a processor supported interface to cache and main memory, with the processor having a multi-stage pipeline for simultaneously executing one pipeline stage for each instruction in the pipeline and with a cycle being the basic instruction processing unit for the processor, an improved method for performing a main memory read and cache refill operation in the event that an instruction reference misses the cache, said method comprising the steps of:
- initiating a pipeline stall during the first cycle subsequent to the cache miss to halt processing of instructions in the pipeline;
- initiating a main memory block read operation;
- reading a block containing a plurality of instructions from said main memory, with said block including said referenced instruction, where the reading step is delayed from the initiating step by a memory latency time interval, where the instructions in said block are sequentially read during successive main memory access cycles staring at a first and ending at a last main memory cycle, and where the referenced instruction is read from main memory during a given main memory access cycle;
- refilling the cache by writing each instruction in the block to the cache during the main memory access cycle in which the instruction is read from main memory;
- initiating a fix-up operation during said given main memory cycle to load the referenced instruction into the pipeline;
- terminating the pipeline stall during the main memory access cycle following the given main memory access cycle to restart the pipeline and to restart processing of the instructions in the block that follow the referenced instruction as they are read from main memory during main memory access cycles;
- loading, during a single cycle, at least one particular instruction, included in said block and which follows said referenced instruction, in said cache, and concurrently loading said particular instruction into the pipeline during said single cycle;
- referencing a first instruction not included in said block of instructions during the last main memory access cycle in which the last instruction of said block is read; and
- processing said first non-block instruction during the cycle following said last main memory access cycle.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 43 U.S. patent(s) that reference this one
|
