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 Title: |
US5204841:
Virtual multi-port RAM
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Chappell, Barbara A.; Amawalk, NY
Chappell, Terry I.; Amawalk, NY
Ebcioglu, Mahmut K.; Somers, NY
Schuster, Stanley E.; Granite Springs, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1993-04-20
/ 1992-04-23
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| Application Number: |
US1992000873672
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| IPC Code: |
Advanced:
G06F 12/04;
G11C 7/10;
G11C 8/12;
G11C 8/16;
G06F 12/08;
Core:
G11C 8/00;
more...
IPC-7:
G11C 8/04;
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| U.S. Class: |
Current:
365/230.05;
365/189.02;
365/189.03;
365/189.05;
365/189.12;
365/203;
365/230.02;
365/230.03;
365/230.06;
365/230.08;
365/233.1;
Original:
365/230.05;
365/189.02;
365/189.03;
365/230.02;
365/230.03;
365/189.05;
365/230.08;
365/233;
365/203;
365/189.12;
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| Field of Search: |
365/189.02,189.03,189.05,230.02,230.03,230.05,230.08,233,203,189.12
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| Priority Number: |
| 1990-07-27 |
US1990000558994 |
| 1992-04-23 |
US1992000873672 |
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| Abstract: |
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
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| Attorney, Agent or Firm: |
Whitham & Marhoefer ;
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| Primary / Asst. Examiners: |
Clawson, Jr., Joseph E.;
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| Maintenance Status: |
E3 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation of copending application Ser. No. 07/558,994 filed Jul. 27, 1990, now abandoned.
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| Designated Country: |
DE FR GB
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| Family: |
Show 8 known family members
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First Claim:
Show all 6 claims |
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:
1. A RAM structure allowing multiple read and write accesses during a machine cycle, said RAM structure being implemented on a semiconductor chip as an array of single-port static RAM cells, said array being divided into one or more sub-arrays, comprising for each sub-array;
- means in the sub-array for generating a release next address signal when a RAM cell within the sub-array has been written or read;
- an on-chip clock circuit responsive to a chip select signal to generate a trigger signal to initiate a first access to said sub-array;
- a plurality of address lines connected to a plurality of address buffers which receive and temporarily store one or more addresses in response to said trigger signal;
- a plurality of address latches connected to receive an output from a corresponding one of said address buffers;
- first circuit means responsive to said release next address signal and to said trigger signal for generating a set-up next signal to said address latches in succession;
- address bus drivers connected to receive an address signal output from any of the address latches for which a set-up next signal has been generated by said first circuit means and in response to said release next address signal from said sub-array, said address bus drivers providing said address signal on an address bus;
- decoder and driver circuit means connected to receive the address signal from said address bus for generating sub-array select, column, wordline, and bitline signals to said sub-array, said decoder and driver circuit means being self-resetting;
- a plurality of data input lines connected to a plurality of data-in buffers which receive and temporarily store one or more data input words in response to said trigger signal;
- a plurality of data-in latches connected to receive an output from a corresponding one of said data-in buffers;
- second circuit means responsive to said trigger signal for generating a set-up next signal to said data-in latches in succession, said second circuit means receiving a release next data-in signal which is derived from said release next address signal;
- data-in bus drivers connected to receive a data-in signal output from any of the data-in latches for which a set-up next signal has been generated by said second circuit means and in response to said release next data-in signal, said data-in bus drivers providing the data-in signal on a data-in bus connected to a write input of the sub-array;
- a plurality of sense amplifiers in the sub-array to output data read out of RAM cells, said plurality of sense amplifiers being connected to a corresponding one of a plurality of data output lines;
- a data-out bus connected to said data output lines to receive data read out of said sub-array;
- a plurality of data-out latches connected to receive data output on said data-out bus, said latches including self-resetting circuit means for resetting a latch upon the latch outputting a data-out signal;
- third circuit means responsive to said trigger signal for generating a set-up next signal to said data-out latches in succession; and
- a plurality of off-chip driver circuits each connected to receive an output from a corresponding one of said data-out latches for which a set-up next signal has been generated by said third circuit means.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 65 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G92-066211
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| Other References: |
"Special Application Memories"; 8172 IEEE International Solid-State Circuits Conference; 28 (1985) Feb.; 32nd Conf.; by Frank E. Barber, Daniel J. Eisenberg, Gloria A. Ingram, Mark S. Strauss and Thomas R. Wik; pp. 44-46.
"Pipelined Clocked Static Memory"; IBM Technical Disclosure Bulletin; vol. 32; No. 38, Aug. 1989, pp. 431-432.
"Pipelined, Time-Sharing Access Technique for a High Integrated Multi-Port Memory"; IEEE Symposium on VLSI Circuits; Jun. 1990; by Tsuneo Matsumura, Ken-ichi Endo and Junzo Yamada; pp. 107-108.
J. Rosenberg, "Dictionary of Computers, Information Processing, and Telecommunications", 2nd Edition, ©1987 John Wiley & Sons, Inc., QA 76,15,R67, pp. 467, 691-693.
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