 |
|
|
|
|
|
 Title: |
US5367648:
General purpose memory access scheme using register-indirect mode
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Chuang, Chiao-Mei; Briarcliff Manor, NY
Ebciogulu, Kemal; Somers, NY
|
| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1994-11-22
/ 1991-02-20
|
| Application Number: |
US1991000659717
|
| IPC Code: |
Advanced:
G06F 9/312;
G06F 9/38;
G06F 12/00;
G06F 12/02;
G06F 13/16;
Core:
more...
IPC-7:
G06F 9/34;
G06F 12/00;
G06F 15/76;
|
| ECLA Code: |
G06F9/312; G06F9/38D; G06F13/16A2C;
|
| U.S. Class: |
Current:
712/225;
711/143;
711/200;
711/211;
712/E09.033;
712/E09.046;
Original:
395/375;
395/400;
395/425;
395/800;
364/247;
364/247.2;
364/255.1;
364/DIG.1;
|
| Field of Search: |
395/375,400,800,425
|
| Priority Number: |
| 1991-02-20 |
US1991000659717 |
|
| Abstract: |
A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance. During memory address generation operations, an arithmetic-logic unit (ALU) generates memory addresses from data in a general purpose register (GPR). Then, the memory addresses are written back to the GPR and a memory address register (MAR). During memory access operations, the MAR is accessed for the memory addresses to access a memory. Two approaches are provided. In a first approach, use of the MAR during the memory access operations is explicit. In a second approach, use of the MAR during the memory access operations is transparent. According to the second approach, a controller is provided to validate the MAR during the memory access operations.
|
| Attorney, Agent or Firm: |
Tassinari, Jr., Robert P. ;
|
| Primary / Asst. Examiners: |
Rudolph, Rebecca L.; Whitefield, Michael A.
|
| Maintenance Status: |
E1 Expired Check current status
CC Certificate of Correction issued
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
| Designated Country: |
DE FR GB IT
|
| Family: |
Show 6 known family members
|
First Claim:
Show all 35 claims |
What is claimed is:
1. A computer system comprising:
- (1) first registers for storing data;
- (2) a second register for storing memory addresses, said second register being architecturally visible such that said second register must be explicitly specified in user-associated instructions to cause memory addresses to be stored in said second register during memory address generation operations;
- (3) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during said memory address generation operations; and
- (4) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers during said memory address generation operations, and for storing said memory addresses in said second register during said memory address generation operations when said second register is explicitly specified in said user-associated instructions.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 5 U.S. patent(s) that reference this one
|
