 |
|
|
|
|
|
 Title: |
US5537341:
Complementary architecture for field-programmable gate arrays
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Rose, Jonathan; Toronto, Canada
Betz, Vaughn; North York, Canada
|
| Assignee: |
Rose; Jonathan, Toronto, Canada
Betz; Vaughn, Toronto, Canada
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1996-07-16
/ 1995-02-10
|
| Application Number: |
US1995000387402
|
| IPC Code: |
Advanced:
G06F 17/50;
Core:
more...
IPC-7:
G06F 17/00;
|
| ECLA Code: |
G06F17/50D4;
|
| U.S. Class: |
Current:
716/016;
Original:
364/579;
|
| Field of Search: |
364/579,578,488,489
|
| Priority Number: |
| 1995-02-10 |
US1995000387402 |
|
| Abstract: |
The use of more than one field-programmable gate array design with a given logic capacity produces advantages over the use of a single field-programmable gate array design. The designs of the field-programmable gate arrays in the family are be selected so that each field-programmable gate array design advantageously implements a different type of circuit. This use can select from the family of FPGAs with the same logic capacity such that the circuits can on average be implemented faster and/or in a smaller area.
|
| Attorney, Agent or Firm: |
Majestic, Parsons, Siebert & Hsue ;
|
| Primary / Asst. Examiners: |
Ramirez, Ellis B.;
|
| INPADOC Legal Status: |
Show legal status actions
|
| Family: |
None
|
First Claim:
Show all 38 claims |
What is claimed is:
1. A method of implementing a digital circuit on a field-programmable gate array comprising the steps of:
- providing a series of field-programmable gate arrays of different designs, at least two of the designs having the same logic capacity, and the designs having sufficient logic capacity to implement the digital circuit wherein the designs are devised such that each design can advantageously implement a subset of all circuit types;
- determining the logic synthesis of the digital circuit into each of the field-programmable gate array designs;
- determining the subsequent placement and routing of the digital circuit into the different designs to select a preferred design of the field-programmable gate arrays for the digital circuit; and
- implementing the digital circuit on a field-programmable gate array of the preferred design.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 33 U.S. patent(s) that reference this one
|
|
|
|
|
|
|
| Foreign References: |
None
|
| Other Abstract Info: |
DERABS G96-341772
DERG96-341772
|
| Other References: |
Quickturn; "RPM Emulation System" 1991.
Walters et al; "Reprogrammable Hardware Emulation Automates System-Lever ASIC Validation"; 1990.
Quickturn; "Logic Emulation For System-Level Design"; 1992.
Varghese et al; "An Efficient Logic Emulation System"; IEEE TRAN. Very Large Scale Integration (VLSI) Systems 1(2) 1993.
Butts et al; "An Efficient Logic Emulation System."; IEEE 1992.
Brown, Stephen, et al.; "A Detailed Router for Field-Programmable Gate Arrays"; IEEE Transactions on Computer-Aided Design; vol. 11, No. 5, May 1992; pp. 620-628.
(9 pages)
Cited by 3 patents
[ISI abstract]
Fawcett, Bradly K.; "Tools to speed FPGA development"; IEEE Spectrum; vol. 31, No. 11, Nov. 1994; pp. 88-94.
(7 pages)
Cited by 2 patents
[ISI abstract]
Rose, Jonathan, et al.; "Architecture of Field-Programmable Gate Arrays"; Proceedings of the IEEE; vol. 81, No. 7; Jul. 1993; pp. 1013-1029.
(17 pages)
Cited by 6 patents
[ISI abstract]
Trimberger, Stephen; "A Reprogrammable Gate Array and Applications"; Proceedings of the IEEE; vol. 81, No. 7; Jul. 1993; pp. 1030-1041.
(12 pages)
Cited by 13 patents
[ISI abstract]
Greene, Jonathan, et al.; "Antifuse Field Programmable Gate Arrays"; Proceedings of the IEEE; vol. 81, No. 7; Jul. 1993; pp. 1042-1056.
(15 pages)
Cited by 31 patents
[ISI abstract]
Sangiovanni-Vincentelli, Alberto, et al.; "Synthesis Methods for Field Programmable Gate Arrays"; vol. 81, No. 7; Jul. 1993; pp. 1057-1083.
(27 pages)
Cited by 3 patents
[ISI abstract]
Chung, Kevin, et al.; "Using Heriarchical Logic Blocks to Improve the Speed of FPGAs"; FPGAs; W. Moore et al., ed.; Abingdon, 1991; pp. 103-113.
Chung, Kevin; "Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections"; Ph.D. Dissertation, University of Toronto; 1992.
He, Jianshe and Jonathan Rose; "Advantages of Heterogeneous Logic Block Architectures for FPGAs"; Custom Integrated Circuits Conference 1993; May, 1993; pp. 7.4.1-7.4.5.
He, Jianshe; "Technology Mapping and Architecture of Heterogeneous Field-Programmable Gate Arrays"; i M.A.Sc. Thesis, University of Toronto; 1994.
|
|
 Nominate this for the Gallery...
|
|
