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 Title: |
US5542067:
Virtual multi-port RAM employing multiple accesses during single machine cycle
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Chappell, Barbara A.; Amawalk, NY
Chappell, Terry I.; Amawalk, NY
Ebcioglu, Mahmut K.; Somers, NY
Schuster, Stanley E.; Granite Springs, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1996-07-30
/ 1994-11-21
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| Application Number: |
US1994000345328
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| IPC Code: |
Advanced:
G11C 7/10;
G11C 8/16;
Core:
G11C 8/00;
more...
IPC-7:
G05F 12/00;
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| ECLA Code: |
G11C7/10M3; G11C7/10S; G11C8/16;
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| U.S. Class: |
Current:
711/167;
365/203;
365/233.1;
365/233.14;
365/233.16;
365/233.17;
711/104;
Original:
395/494;
365/203;
365/233;
364/DIG.1;
364/244.8;
395/431;
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| Field of Search: |
395/401,431,476,494,495,496
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| Priority Number: |
| 1994-11-21 |
US1994000345328 |
| 1992-09-09 |
US1992000942409 |
| 1992-04-23 |
US1992000873672 |
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| Abstract: |
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
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| Attorney, Agent or Firm: |
Whitham, Curtis, Whitham & McGinn ;
Aker, Esq., David ;
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| Primary / Asst. Examiners: |
Kim, Matthew M.;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This is a continuation of U.S. patent application Ser. No. 07/942,409 filed Sep. 9, 1992, now abandoned, which was a divisional of U.S. patent application Ser. No. 07/873,672 filed Apr. 23, 1992, now U.S. Pat. No. 5,204,841.
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| Family: |
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First Claim:
Show all 9 claims |
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:
1. In an array of single port static random access memory (RAM) cells, a method of performing multiple read and write accesses during a single machine cycle of a machine to which said array is coupled, said machine cycle being a basic timing cycle of said machine, said method comprising the steps of:
- temporarily storing a plurality of addresses and data input words;
- selecting one or more RAM cells in said array according to one of said plurality of addresses;
- reading data from or writing data to selected RAM cells according to a read or write input to said array;
- detecting that a RAM cell has been read or written;
- generating a release next cycle signal upon the detection that a RAM cell has been read or written; and
- repeating said steps of selecting, reading or writing, detecting and generating until all temporarily stored addresses have been used to access said array during a machine cycle,
- wherein a multiple cycling of said array of RAM cells is performed during said machine cycle, a timing for said multiple cycling being derived from self-timed signals generated within said array.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
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