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Title: US5542075: Method and apparatus for improving performance of out of sequence load operations in a computer system
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Country: US United States of America

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31 pages

 
Inventor: Ebcioglu, Mahmut K.; Somers, NY
Kronstadt, Eric P.; Katonah, NY
Kumar, Manoj; Yorktown Heights, NY

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 1996-07-30 / 1994-10-07

Application Number: US1994000320111

IPC Code: Advanced: G06F 9/38; G06F 9/45;
Core: more...
IPC-7: G06F 9/30; G06F 9/312; G06F 9/45; G06F 12/02;

ECLA Code: G06F9/38D4; G06F9/45E5;

U.S. Class: Current: 717/151; 712/225; 712/E09.048; 717/154;
Original: 395/700; 364/280.4; 364/280.5; 364/DIG.1; 364/973; 364/DIG.2; 395/800;

Field of Search: 395/650,700,800

Priority Number:
1994-10-07  US1994000320111
1992-05-06  US1992000880102

Abstract: The invention provides for improved performance of out of sequence load operations. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its instruction set, and an address compare unit (ACU). During compilation, the improved compiler identifies load operations that can be move out of sequence ahead of associated store operations and moves those load operations out of sequence and flags them as such. The associated store operations are also flagged. During processor execution of a compiled and optimized program, the address of operands fetched by the out of sequence load operations are saved to the new associative memory. On request, the ACU compares the addresses saved to the addresses generated by the associated store operations. If a comparison results in an identity between the address of a store operation and an address of the out of sequence load operation, a recovery code is run to correct the problem, if not the system continues to execute the program in its compiled order. The system also has the ability to work in a multiprogramming or multitasking environment.

Attorney, Agent or Firm: Heslin & Rothenberg, P.C. ;

Primary / Asst. Examiners: Kriess, Kevin A.; Richey, Michael T.

Maintenance Status: E2 Expired  Check current status

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US1992000880102 1992-05-06       


       
Parent Case:     This application is a continuation of application Ser. No. 07/880,102, filed May 6, 1992.

Designated Country: DE FR GB 

Family: Show 5 known family members

First Claim:
Show all 60 claims
We claim:     1. A method for improving the execution performance of out of sequence load operations with the use of a processor and a dedicated address compare unit (ACU) for comparing a memory address against a stored set of addresses, which method comprises:
  • (a) executing a compiled optimized program with the processor, said complied optimized program having a load operation identified and out of sequence ahead of a store operation, said store operation being identified and preceding said load operation in an uncompiled form of said compiled optimized program, said load operation being out of sequence ahead of said store operation in said compiled optimized program so as to optimize execution performance;
  • (b) saving to the ACU during said executing step (a) an address of an operand fetched by the out of sequence load operation and comparing the saved address with an address generated by the store operation during compiled optimized program execution;
  • (c) if the addresses are different, completing the store operation and continuing said executing step (a) of the compiled optimized program;
  • (d) if the addresses are identical, aborting the store operation and providing for recovery of the program; and
  • wherein execution of said compiled optimized program produces a same output as an execution of said program in a compiled unoptimized form having said load operation in sequence and following said store operation.


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Forward References: Show 24 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (24)   |   Backward references (5)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 27pp US4471433  1984-09 Matsumoto et al.  Tokyo Shibaura Denki Kabushiki Kaisha Branch guess type central processing unit
Buy PDF- 50pp US4847755  1989-07 Morrison et al.  MCC Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
Buy PDF- 9pp US4991090  1991-02 Emma et al.  International Business Machines Corporation Posting out-of-sequence fetches
Buy PDF- 15pp US5173872  1992-12 Crawford et al.  Intel Corporation Content addressable memory for microprocessor system
Buy PDF- 13pp US5202975  1993-04 Rasbold et al.  Supercomputer Systems Limited Partnership Method for optimizing instruction scheduling for a processor having multiple functional resources
       
Foreign References: None

Other Abstract Info: DERABS G93-352991

Other References:
  • Alexandru Nicolau, "Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies", A, May 1989; IEEE Transactions on Computers, vol. 38, No. 5, pp. 663-678. (16 pages) Cited by 4 patents
  • H. T. Kung and John T. Robinson, "On Optimistic Methods for Concurrency Control", Jun. 1981; ACM Transactions on Database Systems, vol. 6, No. 2, pp. 213-226. (14 pages) Cited by 13 patents
  • "Compleat C" by J. F. Peters, III et al, 1986 by Prentice-Hall, pp. 33, 37, and 55.


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