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 Title: |
US5625835:
Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Ebcioglu, Mahmut K.; Somers, NY
Luick, David A.; Rochester, MN
Moreno, Jaime H.; Hartsdale, NY
Silberman, Gabriel M.; Millwood, NY
Winterfield, Philip B.; Rochester, MN
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1997-04-29
/ 1995-05-10
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| Application Number: |
US1995000435411
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| IPC Code: |
Advanced:
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/38;
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| ECLA Code: |
G06F9/38D2; G06F9/312; G06F9/38D4; G06F9/38E2; G06F9/38H2;
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| U.S. Class: |
Current:
712/023;
712/024;
712/244;
712/E09.048;
712/E09.05;
712/E09.061;
Original:
395/800;
395/591;
364/DIG.1;
364/263.2;
364/263;
364/262.4;
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| Field of Search: |
395/800,325
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| Priority Number: |
| 1995-05-10 |
US1995000435411 |
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| Abstract: |
A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.
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| Attorney, Agent or Firm: |
Whitham, Curtis, Whitham & McGinn ;
Tassinari, Jr., Robert P. ;
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| Primary / Asst. Examiners: |
Donaghue, Larry D.;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
DE FR GB
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| Family: |
Show 5 known family members
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First Claim:
Show all 3 claims |
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:
1. A method of reordering memory operations in superscalar or very long instruction word (VLIW) processors even for arbitrarily separated and ambiguous memory references comprising the steps of:
- decoding instructions issued by a processor;
- determining if a decoded instruction is an out-of-order load instruction and, if so, determining if the out-of-order load instruction generates an exception;
- setting a delayed exception bit associated with a target register of the load instruction for an out-of-order load instruction which generates an exception;
- saving a memory address of an out-of-order load instruction which does not generate an exception in an address comparator and setting a valid bit for the saved memory address in the address comparator;
- determining if a decoded instruction is a store operation;
- comparing a range of memory addresses referenced by a decoded store instruction with all entries in the address comparator;
- for each match of an entry in the address comparator, setting the valid bit of the corresponding entry to invalid;
- determining if a decoded instruction is a commit operation;
- checking the valid bit of the address comparator entry associated with a target register of the decoded commit operation and generating a delayed exception if the valid bit is set to invalid and, at the same time, checking the delayed exception bit of a source register of the commit operation and, if the delayed exception bit is set, generating a delayed exception; and
- aborting an excepting instruction and transferring control to an exception handler.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 56 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
K. Diefendorff and M. Allen, "Organization of the Motorola 88110 superscalar RISC microprocessor," IEEE Micro, pp. 40-63, Apr. 1992.
(24 pages)
Cited by 48 patents
[ISI abstract]
K. Ebcioglu et al., "VLIW Compilation techniques in a superscalar environment," in Proc. of the Parallel Architectures and Compiler Technuques PACT '94, 1994.
A. Huang et al., "Speculative disambiguation: a compilation technique for dynamic memory disambiguation," in 21st Intl. Symposium on Computer Architecture, (Chicago, IL) pp. 200-210, 1994.
A. Nicolau, "Run-time disambiguation: coping with statically unpredictable dependencies," IEEE Transactions on Computers, vol. 38, May 1989.
K. Ebcioglu, "Some design ideas for a VLIW architecture for sequential natured software," Parallel Processing (Proceedings of IFIP WG 10.3, Working Conference on Parallel Processing), pp. 3-21, 1988.
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