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 Title: |
US5669001:
Object code compatible representation of very long instruction word programs
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Moreno, Jaime Humberto; Hartsdale, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1997-09-16
/ 1995-03-23
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| Application Number: |
US1995000410431
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| IPC Code: |
Advanced:
G06F 9/38;
G06F 9/45;
Core:
more...
IPC-7:
G06F 9/44;
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| ECLA Code: |
G06F9/38E; G06F9/38E2; G06F9/38E6; G06F9/38T; G06F9/45E5;
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| U.S. Class: |
Current:
717/149;
712/E09.049;
712/E09.05;
712/E09.054;
712/E09.071;
717/155;
Original:
395/706;
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| Field of Search: |
364/DIG. 1 MS File,DIG. 2 MS File
395/376,380,381,382,580,700,705,706,707,708,709,710
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| Priority Number: |
| 1995-03-23 |
US1995000410431 |
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| Abstract: |
Object code compatibility is provided among VLIW processors with different organizations. The object code can be executed by sequential processors, thus providing backward compatibility with scalar and superscalar processors. A mechanism is provided which allows representing VLIW programs in an implementation independent manner. This mechanism relies on instruction cache (I-cache) reload/access processes which incorporate implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation independent manner (i.e., without reflecting the organization of the processor where they are executed), the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. This allows for object code compatibility among VLIW processors with different organizations. This is done by decomposing the process into tasks performed at I-cache reload time and tasks performed at I-cache access time, requiring simpler logic to perform the translation. The resulting VLIWs can be executed starting from any operation within them (e.g., branching into them is possible), and there is a one-to-one correspondence among primitive operations in main memory and in the I-cache. Moreover, a framework is provided for generating (compiling) code which exploits the parallel execution features of a VLIW processor (parallelized code) which is also executable by a sequential processor without unduly affecting performance.
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| Attorney, Agent or Firm: |
Whitham, Curtis, Whitham & McGinn ;
Sbrollini, Jay P. ;
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| Primary / Asst. Examiners: |
Harrell, Robert B.;
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| INPADOC Legal Status: |
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| Designated Country: |
DE FR GB EP JP KR
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| Family: |
Show 11 known family members
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First Claim:
Show all 7 claims |
Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows:
1. A method of storing in computer memory and translating very long instruction words (VLIWs) for execution by VLIW processors with different organizations and providing object code compatibility with scalar and superscalar processors, said method comprising the steps of:
- storing in a computer memory of a processor associated with the computer memory a program to be executed by the processor, the program being stored in the computer memory as a set of tree instructions composed of an unlimited number of internal nodes and an unlimited number of arcs, said internal nodes corresponding to conditional branch instructions and generating two arcs, primitive operations of said processor being associated with said arcs;
- accessing said computer memory to fetch a memory block containing a tree instruction;
- decomposing a fetched tree instruction into a plurality of sequential instructions as variable length VLIWs according to resources of the processor associated with the computer memory and on which the program is to be executed;
- writing the variable length VLIWs in a line of an instruction cache (I-cache) for access by said processor associated with the computer memory; and
- executing by said processor associated with the computer memory the variable length VLIWs written in said I-cache.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 21 U.S. patent(s) that reference this one
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