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 Title: |
US5721854:
Method and apparatus for dynamic conversion of computer instructions
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Ebcioglu, Mahmut Kemal; Somers, NY
Groves, Randall Dean; Austin, TX
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1998-02-24
/ 1996-08-27
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| Application Number: |
US1996000703804
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| IPC Code: |
Advanced:
G06F 9/318;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/45;
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| ECLA Code: |
G06F9/318T; G06F9/38T;
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| U.S. Class: |
Current:
712/203;
712/215;
712/216;
712/E09.037;
712/E09.071;
717/149;
Original:
395/379;
395/706;
395/391;
395/392;
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| Field of Search: |
395/379,382,384,389,390,583,733,391,392,706
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| Priority Number: |
| 1996-08-27 |
US1996000703804 |
| 1995-02-16 |
US1995000390267 |
| 1993-11-02 |
US1993000146547 |
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| Abstract: |
An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.
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| Attorney, Agent or Firm: |
Bailey, Wayne P. ;
McBurney, Mark E. ;
Henkler, Richard A. ;
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| Primary / Asst. Examiners: |
Lall, Parshotam S.; Vu, Viet
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| Maintenance Status: |
E2 Expired Check current status
CC Certificate of Correction issued
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| INPADOC Legal Status: |
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| Related Applications: |
| Application Number |
Filed |
Patent |
Pub. Date |
Title |
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| US1995000390267 | 1995-02-16 |
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| US1993000146547 | 1993-11-02 |
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| Parent Case: |
This is a continuation of application Ser. No. 08/390,267 filed Feb. 16, 1995 now abandoned, which is a continuation of Ser. No. 08/146,547 filed Nov. 2, 1993, now abandoned.
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| Family: |
None
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First Claim:
Show all 2 claims |
We claim:
1. A method of executing a computer program, compiled for sequential instruction execution, on a parallel instruction processing system, the method comprising the steps of:
- retrieving, in response to a cache miss, a group of sequential instructions having a first and second conditional branch instruction, and first and second instructions that are dependent upon the first and second conditional branch instructions, respectively;
- creating a compound instruction for parallel execution including the steps of:
- inserting, for each of the first and second conditional branch instructions, a branch operation, and a branch address, into the compound instruction, the branch condition indicating the condition to be tested, and the branch address indicating where to proceed if the branch is executed;
- inserting, for each of the first and second dependent instructions, a target register, a source operand, an operation indicator, and a dependency indicator, the operation indicator indicating the type of operation to be performed, the source operand indicating the register containing the data for the operation, the target register for containing the result of the operation, and the dependency indicator for indicating whether the execution of the instruction depends upon either the first or second conditional branch instruction; and
- storing the address of the next sequential instruction;
- storing the compound instruction in the cache; and
- indexing the cache according to the address of the first sequential instruction in the compound instruction;
- detecting an exception from the execution of one of the instructions in the compound instruction; and
- executing, in response to the exception, the instructions stored in the compound instruction sequentially.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 40 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G98-168675
DERG98-168675
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| Other References: |
Johnson, "Superscalar Microprocessor Design", Prentice-Hall, 1991, pp. 203-213.
Johnson, "Superscalar Microprocessor Design", Prentice-Hall 1991, pp. 233-235.
Johnson, "Superscalar Microprocessor Design", Prentice-Hall 1991, pp. 25-26.
"Hardware Support for Large Atomic Units in Dynamically Scheduled Machines", Stephen W. Melvin et al, IEEE, 1988, pp. 60-63.
IBM TDB, "Nonredundant Instruction Format for Interpretive Programming Languages", vol. 17, No. 8, Jan. 1975, pp. 2353-2354.
IBM TDB, "Threaded Code Interpreter for Object Code", vol. 28, No. 10, Mar. 1986, pp. 4238-4241.
IEEE 1992, "An Efficient Resource-Constrained Global Scheduling Technique for Superscalar and VLIW Processor", S. Moon and K. Ebcioglu, pp. 55-71.
IEEE 1986, "Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers", Y. Patt et al, pp. 254-258.
ACM 1985, "Critical Issues Regarding HPS, a High Performance Microarchitecture", Y. Patt et al, pp. 109-116.
Computer Society Press of the IEEE, The 14th Annual International Symposium on Computer Architecture Jun. 2-5, 1987, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero", D. R. Ditzel et al, pp. 2-9.
IBM Research Report, RC 16145 (#71759) Oct. 2, 1990, Computer Science, "Some Global Compiler Optimizations and Architectural Features for Improving Performance of Superscalars", K. Ebcioglu et al pp. 1-13.
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