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 Title: |
US5724276:
Logic block structure optimized for sum generation
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Rose, Jonathan S.; Palo Alto, CA
Bauer, Trevor J.; Campbell, CA
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| Assignee: |
Xilinx, Inc., San Jose, CA
other patents from XILINX, INC. (635340) (approx. 867)
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| Published / Filed: |
1998-03-03
/ 1996-06-17
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| Application Number: |
US1996000664628
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| IPC Code: |
Advanced:
G06F 7/50;
G06F 7/505;
G06F 7/575;
Core:
G06F 7/48;
IPC-7:
G06F 7/50;
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| ECLA Code: |
G06F7/503; G06F7/505T; G06F7/575; S06F207/48J5;
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| U.S. Class: |
Current:
708/235;
708/700;
Original:
364/716.06;
364/784.01;
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| Field of Search: |
364/716,768,784,786,785
326/038,39
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| Priority Number: |
| 1996-06-17 |
US1996000664628 |
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| Abstract: |
The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.
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| Attorney, Agent or Firm: |
Young, Edel M. ;
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| Primary / Asst. Examiners: |
Ngo, Chuong Dinh;
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 3 claims |
We claim:
1. A field programmable gate array (FPGA) logic block structure comprising:
- a first multiplexer having at least two data inputs and at least one control input;
- a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer;
- a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer;
- a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and
- a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 51 U.S. patent(s) that reference this one
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