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 Title: |
US5758051:
Method and apparatus for reordering memory operations in a processor
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Moreno, Jaime Humberto; Hartsdale, NY
Moudgill, Mayan; Ossining, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1998-05-26
/ 1996-11-05
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| Application Number: |
US1996000747001
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| IPC Code: |
Advanced:
G06F 9/38;
Core:
more...
IPC-7:
G06F 11/34;
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| ECLA Code: |
G06F9/38D4; G06F9/38H2;
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| U.S. Class: |
Current:
714/002;
712/E09.048;
712/E09.061;
714/050;
714/051;
Original:
395/181;
395/185.03;
395/185.04;
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| Field of Search: |
395/181,183.14,800,735,185.03,185.04
371/67.1
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| Priority Number: |
| 1996-11-05 |
US1996000747001 |
| 1996-07-30 |
US1996000688076 |
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| Abstract: |
A computer processing system stores sequences of instructions in a memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. Such out-of-order load instruction identifies a location in memory from which to read a datum and a first destination register in which to place the datum. The present invention is a method and corresponding apparatus that utilizes data comparison to detect coherence among memory and the datum read by an out-of-order load operation. More specifically, the method consists of an interference test which controls the processor unit to read a datum from the same location in memory identified by the out-of-order load instruction and compare the newly read datum with the datum saved in the first destination register. If the values do not match, the newly read datum is placed in a second destination register and a recovery sequence is executed. The second destination register may be identical to the first destination register. The invention is applicable to static and dynamic reordering of instructions, and can be implemented using instructions or using hardware resources.
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| Attorney, Agent or Firm: |
Sbrollini, Jay P. ;
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| Primary / Asst. Examiners: |
Chung, Phung M.;
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| INPADOC Legal Status: |
Show legal status actions
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| Parent Case: |
The present invention is a continuation-in-part of U.S. patent application Ser. No. 08/688,076 filed on Jul., 30, 1996, now abandoned, herein incorporated by reference in its entirety.
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| Family: |
None
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First Claim:
Show all 32 claims |
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:
1. In a computer processing system wherein sequences of instructions are executed by a processor unit, wherein at least one of said instructions is a load instruction that is moved from an original position in said sequences of instructions to an earlier position in said sequences of instructions, and wherein said at least one load instruction is moved over at least one store instruction thereby becoming an out-of-order load instruction, wherein said out-of-order load instruction identifies a location in a memory subsystem from which to read a first data and a first target register in which to place the data, a method for determining coherence among data in the first target register and the memory subsystem, the method comprising the steps of:
- executing said out-of-order load instruction which controls said processor unit to read said first data from said location in memory identified by said out-of order load instruction and place said first data in said first target register identified by said out-of-order load instruction;
- after performing said at least one store instruction, controlling said processor unit to perform the following steps:
- reading second data from the same location in memory identified by said out-of-order load instruction,
- comparing said second data to said first data placed in said first target register, and executing a recovery sequence if said second data is not equal to said first data.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 33 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
IEEE Micro, IEEE Computer Society, Apr. 1992, pp. 40-63, "Organization of the Motorola 88110 Superscalar Risc Microprocessor", K. Diefendorff, M. Allen.
(24 pages)
Cited by 48 patents
[ISI abstract]
Proceedings 1986 Sigplan Symposium on Compiler Construction vol. 21, No. Jul. 1986, pp. 11-16, "Efficient Instruction Scheduling for a Pipelined Architecture" P. B. Gibbons, S. S. Muchnick.
(6 pages)
Cited by 7 patents
AGM Sigplan Notices, vol. 25, No. 7, Jul. 1990, pp. 97-106, "Brief Summary Papers on Scheduling for Pipeline Processors", S. Krishnamurthy.
(10 pages)
Cited by 4 patents
Dept. of Computer Science, Cornell Univ., May, 1985, "Percolation Scheduling: A Parallel Compilation Technque", Alexandru Nicolau.
IEEE Transactions on Computers, vol. 38, No. 5, May 1989, pp. 663-678, Run Time Disambiguation: Coping with Statically Unpredictable Dependencies, Alexandru Nicolau.
(16 pages)
Cited by 4 patents
Annual International Symposium on Computer Architecture 1994, IEEE Computer Society Press, pp. 200-210, Speculatives Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation, A. S. Huang, G. Slavenberg, J. P. Shen.
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