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Title: US5799179: Handling of exceptions in speculative instructions
[ Derwent Title ]


Country: US United States of America

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18 pages

 
Inventor: Ebcioglu, Kemal; Somers, NY
Silberman, Gabriel Mauricio; Millwood, NY

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 1998-08-25 / 1995-01-24

Application Number: US1995000377563

IPC Code: Advanced: G06F 9/38;
Core: more...
IPC-7: G06F 9/00;

ECLA Code: G06F9/38E2; G06F9/38H2;

U.S. Class: Current: 712/234; 712/216; 712/E09.05; 712/E09.061;
Original: 395/581; 395/392;

Field of Search: 395/375,800,581,392

Priority Number:
1995-01-24  US1995000377563

Abstract: CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions, and resolving (204) these exceptions by correcting (206) what caused the exception and re-executing (208) the instructions which are known to be in a taken path. Tracking speculative exceptions has two components which use an exception bit which is set in response to an exception condition (213). The invention tracks an original speculative exception which occurs when a speculative instruction whose operand(s) do not have any exception bits set encounters an exception condition. Speculative exception resolution is triggered when a non-speculative instruction--which is in the taken path of a conditional branch--uses an operand from a register having its exception bit set. The presence of an exception condition and a non-speculative instruction yields an exception signal (220) to exception resolution (204). Speculative exception resolution (204) includes responding to output signals from the extra register and extra exception bit for correcting (204) the exception condition which caused the exception and re-executing (208) the instructions which depended on the results of the instructions causing the speculative exception. This invention also handles the case where a speculative instruction attempts to use a register having its exception bit set as above.

Attorney, Agent or Firm: Perman & Green, LLP ;

Primary / Asst. Examiners: Lall, Parshotam S.; Coulter, Kenneth R.

Maintenance Status: CC Certificate of Correction issued

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Designated Country: CA CN CZ EP HU JP KR PL RU  DE FR GB 

Family: Show 16 known family members

First Claim:
Show all 59 claims
We claim:     1. A method for handling speculative exceptions while parallel processing sequential code, comprising the steps:
  • speculatively executing one or more instructions;
  • tracking a speculative exception caused by a speculative instruction; and
  • subsequently resolving the speculative exception by correcting for the exception condition and re-executing only the speculative instruction and any speculative instructions that are dependent on the speculative instruction.


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Forward References: Show 18 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (18)   |   Backward references (12)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 20pp US4539635  1985-09 Boddie et al.  AT&T Bell Laboratories Pipelined digital processor arranged for conditional operation
Buy PDF- 25pp US5299318  1994-03 Bernard et al.  Bull S.A. Processor with a plurality of microprogrammed units, with anticipated execution indicators and means for executing instructions in pipeline manner
Buy PDF- 13pp US5303355  1994-04 Gergen et al.  Motorola, Inc. Pipelined data processor which conditionally executes a predetermined looping instruction in hardware
Buy PDF- 17pp US5421022  1995-05 McKeen et al.  Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
Buy PDF- 16pp US5428807  1995-06 McKeen et al.  Digital Equipment Corporation Method and apparatus for propagating exception conditions of a computer system
Buy PDF- 7pp US5479616  1995-12 Garibay et al.  Cyrix Corporation Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception
Buy PDF- 12pp US5537559  1996-07 Kane et al.  Meridian Semiconductor, Inc. Exception handling circuit and method
Buy PDF- 23pp US5561776  1996-10 Popescu et al.  Hyundai Electronics America Processor architecture supporting multiple speculative branching
Buy PDF- 17pp US5584001  1996-12 Hoyt et al.  Intel Corporation Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history
Buy PDF- 21pp US5592636  1997-01 Popescu et al.  Hyundai Electronics America Processor architecture supporting multiple speculative branches and trap handling
Buy PDF- 18pp US5634023  1997-05 Adler et al.  Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions
Buy PDF- 112pp US5651124  1997-07 Shen et al.  HAL Computer Systems, Inc. Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state
       
Foreign References: None

Other Abstract Info: DERABS G1996-362837

Other References:
  • K. Ebcioglu, "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software", Proc. IFIP WG10.3 Working Conf. on Parallel Processing, North Holland, 1988, pp. 3-21.
  • R. Cohn, T. Gross, M. Lam, and P.S. Tseng, "Architecture and Complier Tradeoffs for a Long Instruction Word Microprocessor," Proc. 3rd Intl Conf. on Architectural Support for Programming Languages and Operating Systems, Boston, MA, Apr. 1989, pp. 2-14.
  • R.P. Colwell et al., "A VLIW Architecture for a Trace Scheduling Complier," IEEE Transactions on Computers vol. 37, No. 8, Aug. 1988, pp. 967-979. (13 pages) Cited by 31 patents
  • R.D. Groves and R. Oehler, "An IBM Second Generation RISC Processor Architecture," Proc. IEEE Intl Conf. on Computer Design, Oct. 1989, pp. 134-137.
  • "Metaflow Targets SPARC and 386 with Parallel Architecture," Microprocessor Report, Dec. 1988.
  • T.S. Perry, "Intel's Secret is Out," IEEE Spectrum, vol. 26, No. 4, Apr. 1989, pp. 22-28. (7 pages)
  • J.E. Smith, "Dynamic Instruction Scheduling and the Astronauties ZS-1," IEEE Computer, vol. 22, No. 7, Jul. 1989, pp. 21-35. (15 pages) Cited by 32 patents
  • M.D. Smith, M.S. Lam, and M.A. Horowitz, "Boosting Beyond Static Scheduling in a Superscalar Processor," Proc. 17th International Symp. on Computer Architecture, Seattle, WA, May 1990, pp. 344-354.
  • K. Ebcioglu and T. Nakatani, "A New Compiliation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture," Proc. Workshop on Languages and Compliers for Parallell Computing, Urbana, IL, MIT Press Research Monograph In Parallel and Distributed Computing, D. Gelernter et al, editors, Aug. 1989, pp. 213-229.
  • M.C. Golumbic and V. Rainish, "Instruction Scheduling Beyond Basic Blocks," IBM J. of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 93-97. (5 pages) Cited by 3 patents
  • K. Ekanadham and R. Rechtschaffen, "Speculation in Parallel Systems", IBM Technical Disclosure Bulletin, vol. 36, No. 09A, Sep. 1993, pp. 371-376.
  • T. Nakatani and K. Ebcioglu, "Using a Lookahead Window in a Compaction Based Parallelizing Complier," Proc. 23rd Workshop on Microprogramming and Microarchitecture, IEEE Computer Society Press, Nov. 1990, pp. 57-68.
  • K. Ebcioglu and R. Groves, "Some Global Complier Optimizations and Architectural Features for Improving Performance of Superscalars," Research Report RC 16145 IBM T.J. Watson Research Center, Feb. 1990.
  • K. Ekanadham and R. Rechtschaffen, "Metaparallelism-Communication via Placeholders", IBM Technical Disclosure Bulletin, vol. 36, No. 09B, Sep. 1993, pp. 285-288.
  • T.N. Hicks, "Data Restoration of an Addressable Array", IBM Technical Disclosure Bulletin, vol. 35, No. 1A Jun. 1992, pp. 222-225.
  • J.E. Smith and A.R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, vol. 37, No. 5, May 1988, pp. 562-573. (12 pages) Cited by 92 patents
  • David Bernstein, Michael Rodch, Mooly Sagiv, "Proving Safety of Speculative Load Instructions at Compile-Time", IBM Israel Scientific Center, Lecture Notes in Computer Science, 4th European Symposium on Programming Feb. 1992, pp. 56-72. (17 pages) [ISI abstract]


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