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 Title: |
US5844422:
State saving and restoration in reprogrammable FPGAs
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Trimberger, Stephen M.; San Jose, CA
Rose, Jonathan S.; Toronto, Canada
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| Assignee: |
Xilinx, Inc., San Jose, CA
other patents from XILINX, INC. (635340) (approx. 867)
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| Published / Filed: |
1998-12-01
/ 1996-11-13
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| Application Number: |
US1996000748443
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| IPC Code: |
Advanced:
H03K 19/177;
Core:
more...
IPC-7:
H03K 19/173;
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| ECLA Code: |
H03K19/177;
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| U.S. Class: |
Current:
326/038;
326/040;
Original:
326/038;
326/040;
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| Field of Search: |
326/038,39,40
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| Priority Number: |
| 1996-11-13 |
US1996000748443 |
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| Abstract: |
Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described. These include: (1) bits in the bitstream of a first configuration which indicate which memory units of the first configuration are to be retained during a second configuration; (2) bits at the beginning of the bitstream of a second configuration which indicate which memory units of the first configuration are to be retained during a second configuration; and (3) circuit loadable during operation of a first configuration which indicates which memory units of the first configuration are to be retained during a second configuration.
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| Attorney, Agent or Firm: |
Young, Edel M. ;
Tachner, Adam H. ;
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| Primary / Asst. Examiners: |
Westin, Edward P.; Le, Dom
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 24 claims |
We claim:
1. A field-programmable gate array (FPGA) with state saving comprising:
- a plurality of logic blocks for generating logic functions;
- a plurality of registers for storing data generated by said logic functions, each of said registers having one or more states representative of said stored data;
- an interconnect structure for interconnecting said logic blocks and said registers;
- configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user; and
- state saving means for preventing said configuration means from changing the states of at least some of said registers which store said data.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 68 U.S. patent(s) that reference this one
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| Foreign References: |
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PDF |
Publication |
Date |
IPC Code |
Assignee |
Title |
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JP1988245016(A)
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1988-12 |
H03K 19/177
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| Other Abstract Info: |
DERABS G1999-044779
DERABS G1999-044779
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| Other References: |
Xilinx, Inc., "The Programmable Logic data Book," 1994, 2-7 through 2-49, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
S. Wilton, J. Rose, Z. Vranesic, "Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays", IEEE CICC, May 1996, pp. 144-147.
T. Ngai, J. Rose, S. Wilton, "An SRAM-Programmable Field-Configurable Memory", IEEE CICC, Santa Clara, CA May 1995, pp. 499-502.
S. Wilton, J. Rose, Z. Vranesic, "Architecture of Centralized Field-Configurable Memory", 3rd ACM Int'l Symposium on Field-Programmable Gate-Arrays, FPGA '95, Feb. 1995, pp. 97-103.
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