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 Title: |
US5918005:
Apparatus region-based detection of interference among reordered memory operations in a processor
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Moreno, Jaime Humberto; Hartsdale, NY
Moudgill, Mavan; Ossining, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1999-06-29
/ 1997-03-25
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| Application Number: |
US1997000827016
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| IPC Code: |
Advanced:
G06F 9/38;
Core:
more...
IPC-7:
G06F 11/25;
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| U.S. Class: |
Current:
714/038;
712/E09.048;
Original:
395/183.14;
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| Field of Search: |
395/183.14,800.23,709,392
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| Priority Number: |
| 1997-03-25 |
US1997000827016 |
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| Abstract: |
The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.
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| Attorney, Agent or Firm: |
Sbrollini, Jay P. ;
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| Primary / Asst. Examiners: |
Beausoliel, Jr., Robert W.; Elisca, Pierre E.
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
Show 12 known family members
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First Claim:
Show all 27 claims |
What is claimed is:
1. In a computer processing system wherein sequences of instructions are executed by a processor unit, wherein at least one of said instructions is a load instruction that is moved from an original position in said sequences of instructions to an earlier position in said sequences of instructions, and wherein said at least one load instruction is moved over at least one store instruction thereby becoming an out-of-order load instruction, wherein said out-of-order load instruction identifies a location in a memory subsystem from which to read data and said at least one store instruction identifies a location in the memory subsystem where to store data, a method for detecting interference between said out-of-order load instruction and said at least one store instruction, and for recovering from such interference, the method comprising the steps of:
- storing in a table a plurality of entries, wherein each entry E corresponds to at least one region R of a plurality of regions of said memory subsystem, wherein each region of said memory subsystem encompasses a plurality of locations that may be accessed by out-of-order load instructions and store instructions wherein said entry E includes at least one field that indicates:
- (i) whether said processor unit is processing at least one out-of-order load instruction that loads data from a location within said region R, and
- ii) whether said processor unit is processing at least one interfering store instruction that stores data to a location within said region R, wherein said interfering store instruction interferes with an out-of-order load instruction that loads data from a location within said region R;
- identifying an entry E1 corresponding to a first out-of-order load instruction being processed by said processing unit, wherein said entry E1 corresponds to a region R1 of said memory subsystem and said first out-of-order load instruction loads data from a location within said region R1;
- upon reaching said original position of said first out-of-order load instruction, controlling said processor unit to execute a recovery sequence if said at least one field of an entry E1 indicates that said processor unit is processing at least one interfering store instruction that stores data to a location within said region R1.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 13 U.S. patent(s) that reference this one
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