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 Title: |
US5951674:
Object-code compatible representation of very long instruction word programs
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Moreno, Jaime Humberto; Hartsdale, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1999-09-14
/ 1996-02-14
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| Application Number: |
US1996000601640
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| IPC Code: |
Advanced:
G06F 9/38;
G06F 9/45;
Core:
more...
IPC-7:
G06F 9/45;
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| ECLA Code: |
G06F9/38E; G06F9/38E2; G06F9/38E6; G06F9/38T; G06F9/45E5;
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| U.S. Class: |
Current:
712/210;
712/200;
712/E09.049;
712/E09.05;
712/E09.054;
712/E09.071;
Original:
712/210;
712/200;
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| Field of Search: |
395/376,380,386
712/210,200
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| Priority Number: |
| 1996-02-14 |
US1996000601640 |
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| Abstract: |
Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors, A mechanism is provided which allows representing VLIW programs in an implementation-independent manner. This mechanism relies on instruction cache (I-cache) reload/access logic which incorporates implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation-independent manner, the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. The foregoing allows for object-code compatibility among VLIW processors with different organizations. Also provided is a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor.
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| Attorney, Agent or Firm: |
Ratner & Presita ;
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| Primary / Asst. Examiners: |
Maung, Zarni; Najjar, Saleh
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Parent Case: |
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a continuation-in-part of U.S. application Ser. No. 08/410,431, filed Mar. 23, 1995, entitled "Object Code Compatible Representation of Very Long Instruction Word Programs", now U.S. Pat. No. 5,669,001.
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| Designated Country: |
DE FR GB EP JP KR
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| Family: |
Show 11 known family members
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First Claim:
Show all 53 claims |
Having thus described my invention, what I claim and desire to secure by Letters Patent is as follows:
1. A method of executing a program, said method comprising the steps of:
- constructing a program as a set of variable length tree-instructions, each given tree-instruction comprising a sequence of primitive instructions including at least one execution path which are subject to sequential semantics, wherein each execution path starting at a first primitive instruction of said sequence of primitive instructions for said given tree-instruction and terminating at an unconditional branch instruction to a target instruction outside of said tree-instruction;
- storing said program in memory, wherein, for each given tree-instruction, said sequence of primitive instructions for said given tree-instruction are stored in consecutive memory locations;
- accessing said memory to fetch a memory block;
- decomposing portions of at least one tree-instruction stored in said memory block into a plurality of variable length intermediate instructions according to resources of a processor;
- executing said variable-length intermediate instructions in said processor.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 23 U.S. patent(s) that reference this one
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| Foreign References: |
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Publication |
Date |
IPC Code |
Assignee |
Title |
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JP05289870
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1993-05 |
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| Other Abstract Info: |
DERABS G1996-443356
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| Other References: |
IEEE, vol. 37, No. 8, Aug. 1988, "A VLIW Architecture for a Trace Scheduling Compiler", R. Colwell et al., pp. 967-979.
(13 pages)
Cited by 31 patents
The Journal of Supercomputing, 7, 1993, "The Cydra 5 Minisupercomputer: Architecture and Implementation", G. R. Beck et al., pp. 143-180.
(38 pages)
Cited by 12 patents
[ISI abstract]
IEEE, Sep. 1981, "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family", A. E. Charlesworth, pp. 18-27.
Cited by 57 patents
K. Ebcioglu, "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software", pp. 3-21, Proceedings of the IFIP WG 10.3 Working Conference on Parallel Processing, Pisa, Italy, Apr. 25-27 1988.
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