Work Files Saved Searches
   My Account                                                  Search:   Quick/Number   Boolean   Advanced   Derwent    Help   


 The Delphion Integrated View

  Buy Now:   Buy PDF- 23pp  PDF  |   File History  |   Other choices   
  Tools:  Citation Link  |  Add to Work File:    
  View:  Expand Details   |  INPADOC   |  Jump to: 
  Go to:  Derwent  
 Email this to a friend  Email this to a friend 
       
Title: US6189088: Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location
[ Derwent Title ]


Country: US United States of America

View Images High
Resolution

 Low
 Resolution

 
23 pages

 
Inventor: Gschwind, Michael K.; Danbury, CT

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
 News, Profiles, Stocks and More about this company

Published / Filed: 2001-02-13 / 1999-02-03

Application Number: US1999000243721

IPC Code: Advanced: G06F 9/318; G06F 9/38; G06F 9/45;
Core: more...
IPC-7: G06F 9/312;

ECLA Code: G06F9/318; G06F9/38D4; G06F9/38E2; G06F9/45E5;

U.S. Class: Current: 712/216; 712/023; 712/225; 712/E09.035; 712/E09.048; 712/E09.05;
Original: 712/216; 712/023; 712/225;

Field of Search: 712/023,216,225

Priority Number:
1999-02-03  US1999000243721

Abstract: The present invention is directed to method and apparatus for reordering load operations in a computer processing system. In one aspect of the invention, a method for scheduling instructions for execution in a computer processing system implementing out-of-order execution, includes the steps of: selecting and moving a next instruction from its current position in a sequence of instructions to an earlier position; determining whether the selected instruction may reference a memory location for read-access; determining whether non-selected instructions, which may ambiguously reference the memory location for read-access, were previously moved over the selected instruction, when the selected instruction may reference the memory location for read-access; establishing a bypass sequence to be performed during an execution of the selected instruction and which passes data previously read-accessed by the non-selected instructions to the selected instruction, when the non-selected instructions were previously moved over the selected instruction and addresses of memory locations from which the non-selected instructions have read-accessed the data are the same as an address of the memory location from which the selected instruction is to read-access data; determining whether the selected instruction was previously moved over the non-selected instructions, when the selected instruction may reference the memory location for read-access; and adding a mechanism for storing a record of the selected instruction for future reference by the non-selected instructions.

Attorney, Agent or Firm: F. Chau & Associates, LLP ;

Primary / Asst. Examiners: Kim, Kenneth S.;

Maintenance Status: E1 Expired  Check current status

INPADOC Legal Status: Show legal status actions          Buy Now: Family Legal Status Report

Family: Show 5 known family members

First Claim:
Show all 37 claims
What is claimed is:     1. A method for scheduling instructions for execution in a computer processing system implementing out-of-order execution, the method comprising the steps of:
  • selecting and moving a next instruction from its current position in a sequence of instructions to an earlier position;
  • determining whether the selected instruction may reference a memory location for read-access;
  • determining whether non-selected instructions, which may ambiguously reference the memory location for read-access, were previously moved over the selected instruction, when the selected instruction may reference the memory location for read-access;
  • establishing a bypass sequence to be performed during an execution of the selected instruction and which passes data previously read-accessed by the non-selected instructions to the selected instruction, when the non-selected instructions were previously moved over the selected instruction and addresses of memory locations from which the non-selected instructions have read-accessed the data are the same as an address of the memory location from which the selected instruction is to read-access data;
  • determining whether the selected instruction was previously moved over the non-selected instructions, when the selected instruction may reference the memory location for read-access; and
  • adding a mechanism for storing a record of the selected instruction for future reference by the non-selected instructions.


Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 11 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (11)   |   Backward references (7)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 16pp US5420990  1995-05 McKeen et al.  Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
Buy PDF- 17pp US5421022  1995-05 McKeen et al.  Digital Equipment Corporation Apparatus and method for speculatively executing instructions in a computer system
Buy PDF- 31pp US5542075  1996-07 Ebcioglu et al.  International Business Machines Corporation Method and apparatus for improving performance of out of sequence load operations in a computer system
Buy PDF- 20pp US5606670  1997-02 Abramson et al.  Intel Corporation Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system
Buy PDF- 12pp US5689712  1997-11 Heisch  International Business Machines Corporation Profile-based optimizing postprocessors for data references
Buy PDF- 30pp US5758081  1998-05 Aytac   Computing and communications transmitting, receiving system, with a push button interface, that is continously on, that pairs up with a personal computer and carries out mainly communications related routine tasks
Buy PDF- 27pp US5960467  1999-09 Mahalingaiah et al.  Advanced Micro Devices, Inc. Apparatus for efficiently providing memory operands for instructions
       
Foreign References:
Buy
PDF
Publication Date IPC Code Assignee   Title
Buy PDF- 12pp EP0709770 1996-05  G06F 9/38 International Business Machines Corporation Apparatus to control load/store instructions 
Buy PDF- 13pp EP0742512 1996-11  G06F 9/38 IBM Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor 
Buy PDF- 28pp GB2265481 1993-09  G06F 9/312 * HEWLETT-PACKARD COMPANY MEMORY PROCESSOR THAT PERMITS AGGRESSIVE EXECUTION OF LOAD INSTRUCTIONS 


Other Abstract Info: DERABS G2000-568350

Other References:
  • Diefendorff, et al., "Organization of the Motorola 88110 Superscaler RISC Microprocessor", 1992 IEEE Micro, pp. 40-63. (24 pages) Cited by 48 patents [ISI abstract]


  • Inquire Regarding Licensing

    Powered by Verity


    Plaques from Patent Awards      Gallery of Obscure PatentsNominate this for the Gallery...

    Thomson Reuters Copyright © 1997-2010 Thomson Reuters 
    Subscriptions  |  Web Seminars  |  Privacy  |  Terms & Conditions  |  Site Map  |  Contact Us  |  Help