Pipeline control for high-frequency pipelined designs (US6192466)

Patent	Pub.Date	Inventor	Assignee	Title
US5075844	1991-12	Jardine et al.	Tandem Computers Incorporated	Paired instruction processor precise exception handling mechanism
US5185872	1993-02	Arnold et al.	Intel Corporation	System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy
US5572690	1996-11	Molnar et al.	Sun Microsystems, Inc.	Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions
US5574925	1996-11	Paver	The Victoria University of Manchester	Asynchronous pipeline having condition detection among stages in the pipeline
US5600848	1997-02	Sproull et al.	Sun Microsystems, Inc.	Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction
US5666506	1997-09	Hesson et al.	International Business Machines Corporation	Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
US5887152	1999-03	Tran	Advanced Micro Devices, Inc.	Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
US5987594	1999-11	Panwar et al.	Sun Microsystems, Inc.	Apparatus for executing coded dependent instructions having variable latencies
US6006030	1999-12	Dockser	VLSI Technology, Inc.	Microprocessor with programmable instruction trap for deimplementing instructions
US6009506	1999-12	Jardine et al.	Tandem Computers Incorporated	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions
US6052775	2000-04	Panwar et al.	Sun Microsystems, Inc.	Method for non-intrusive cache fills and handling of load misses
USH1291	1994-02	Hinton et al.		Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions


	Foreign References:			None
	Other References:			Sproull et al., "The Counterflow Pipeline Processro Architecture," IEEE Design & Test of Computers, pp. 48-59, 1994. (12 pages) Cited by 9 patents [ISI abstract] Moudgill et al., "Register Renaming and Dynamic Speculation: an Alternatice Approach," IEEE, pp. 202-213, 1993. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, No. 6, pp. 720-738, Jun. 1989. (19 pages) Cited by 21 patents Woods et al., "AMULET 1: An Asynchronous ARM Microprocessor," IEEE Transactions on Computers, vol. 46, No. 4, pp. 385-398, Apr. 1997. (14 pages) [ISI abstract] Richardson et al., "Fred: An Architecture for a Self-Timed Decoupled Computer," IEEE, pp. 60-68, 1996. Richardson et al., "Precise Exception Handling for a Self-Timed Processor," IEEE, pp. 32-37, 1995. Gschwind, Dissertation, "Hardware/Software Co-Evaluation of Instruction Sets," pp. 1-115, Apr. 1996.
				Nominate this for the Gallery...


		Copyright © 1997-2010 Thomson Reuters
		Subscriptions \| Web Seminars \| Privacy \| Terms & Conditions \| Site Map \| Contact Us \| Help