Heterogeneous interconnection architecture for programmable logic devices (US6590419)

a first group of signal wires each having a first width, said first group of signal wires connected to a first subplurality of said function blocks in accordance with a first operational parameter; and

a second group of signal wires each having a second width different than said first width, said second group of signal wires connected to a second subplurality of said function blocks in accordance with a second operational parameter; wherein:

said first operational parameter comprises signal propagation speed, and

said second operational parameter comprises circuit area.

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