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Title: US6604230: Multi-logic device systems having partial crossbar and direct interconnection architectures
[ Derwent Title ]

Country: US United States of America

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22 pages

 
Inventor: Khalid, Mohammed A. S.; Santa Clara, CA
Rose, Jonathan; Toronto, Canada

Assignee: The Governing Counsel of the University of Toronto, Toronto, Canada
other patents from GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO (229425) (approx. 39)
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Published / Filed: 2003-08-05 / 1999-02-09

Application Number: US1999000248084
IPC Code: Advanced: G06F 15/78; G06F 17/50;
Core: G06F 15/76; more...
IPC-7: G06F 17/50;

ECLA Code: G06F15/78R; G06F17/50C3E;

U.S. Class: 716/016; 716/017; 716/012; 326/038; 326/047; 326/101;

Field of Search: 716/016,17,15,4 703/023 326/036,38,39,41,47,101

Priority Number:
1999-02-09  US1999000248084

Abstract:     Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. The architecture disclosed uses a mixture of hardwired and programmable connections for interconnecting the FPGAs. A hardwired connection is a direct connection between a pair of FPGA I/O pins. A programmable connection refers to the scheme in which pair of FPGA I/O pins are connected using an programmable interconnect device. In the architecture disclosed, the I/O pins in each FPGA are divided into two groups: hardwired connections and programmable connections. The pins in the first group connect to other FPGAs and the pins in the second group connect to FPIDs. The FPGAs and FPIDs are interconnected using a partial crossbar architecture.

Attorney, Agent or Firm: Orrick, Herrington & Sutcliffe LLP ;

Primary / Asst. Examiners: Siek, Vuthe;

INPADOC Legal Status: Show legal status actions

Family: None
First Claim:
Show all 13 claims		 What is claimed is:     1. An electrically reconfigurable logic assembly comprising:
  • a printed circuit board, said printed circuit board comprising a plurality of fixed electrical conductors, said plurality of fixed electrical conductors segregated into at least a first set of fixed electrical conductors and a second set of fixed electrical conductors;
  • a plurality of reprogrammable logic devices disposed on said printed circuit board, each of said plurality of reprogrammable logic devices comprising configurable logic elements, each of said plurality of reprogrammable logic devices also comprising logic device input/output terminals, said logic device input/output terminals reprogrammably connectable to selected ones of said plurality of configurable logic elements;
  • a plurality of reprogrammable interconnect devices disposed on said printed circuit board, each of said reprogrammable interconnect devices having interconnect device input/output terminals and internal circuitry, said internal circuitry reprogrammably configurable to provide interconnections between selected ones of said interconnect device input/output terminals;
  • said first set of fixed electrical conductors connecting a first group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said interconnect device input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said first group of said logic device input/output terminal on each of said plurality of reprogrammable logic devices; and
  • said second set of fixed electrical conductors connecting a second group of said logic device input/output terminals on said plurality of reprogrammable logic devices to said second group of logic device input/output terminals on every other of said plurality of reprogrammable logic devices, such that each of said plurality of reprogrammable logic devices is in direct electrical communication with every other of said plurality of reprogrammable logic devices on said printed circuit board.
    •


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Forward References: Show 5 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (5)   |   Backward references (29)   |   Citation Link

Buy
PDF		 Patent  Pub.Date  Inventor Assignee   Title
  US3473160  1969-10 Wahlstrom   ELECTRONICALLY CONTROLLED MICROELECTRONIC CELLULAR LOGIC ARRAY
Buy PDF- 17pp US4539564  1985-09 Smithson   Electronically controlled interconnection system
Buy PDF- 22pp US4642487  1987-02 Carter  Xilinx, Inc. Special interconnect for configurable logic array
Buy PDF- 14pp US4695999  1987-09 Lebizay  International Business Machines Corporation Cross-point switch of multiple autonomous planes
Buy PDF- 17pp US4697241  1987-09 Lavi  Simulog, Inc. Hardware logic simulator
Buy PDF- 23pp US4914612  1990-04 Beece et al.  International Business Machines Corporation Massively distributed simulation engine
Buy PDF- 34pp US4935734  1990-06 Austin  Pilkington Micro-Electronics Limited Semi-conductor integrated circuits/systems
Buy PDF- 97pp US5036473  1991-07 Butts et al.  Mentor Graphics Corporation Method of using electronically reconfigurable logic circuits
Buy PDF- 26pp US5109353  1992-04 Sample et al.  Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
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Buy PDF- 31pp US5329470  1994-07 Sample et al.  Quickturn Systems, Inc. Reconfigurable hardware emulation system
Buy PDF- 13pp US5352123  1994-10 Sample et al.  Quickturn Systems, Incorporated Switching midplane and interconnection system for interconnecting large numbers of signals
Buy PDF- 27pp US5386550  1995-01 Yumioka et al.  Fujitsu Limited Pseudo-LSI device and debugging system incorporating same
Buy PDF- 13pp US5414638  1995-05 Verheyen et al.  Aptix Corporation Programmable interconnect architecture
Buy PDF- 99pp US5448496  1995-09 Butts et al.  Quickturn Design Systems, Inc. Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
Buy PDF- 99pp US5452231  1995-09 Butts et al.  Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
Buy PDF- 131pp US5452239  1995-09 Dai et al.  Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
Buy PDF- 23pp US5475830  1995-12 Chen et al.  Quickturn Design Systems, Inc. Structure and method for providing a reconfigurable emulation circuit without hold time violations
Buy PDF- 31pp US5544069  1996-08 Mohsen  Aptix Corporation Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components
Buy PDF- 20pp US5551013  1996-08 Beausoleil et al.  International Business Machines Corporation Multiprocessor for hardware emulation
Buy PDF- 71pp US5572710  1996-11 Asano et al.  Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
Buy PDF- 22pp US5574388  1996-11 Barbier et al.  Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
Buy PDF- 15pp US5596742  1997-01 Agarwal et al.  Massachusetts Institute of Technology Virtual interconnections for reconfigurable logic systems
Buy PDF- 27pp US5649176  1997-07 Selvidge et al.  Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
Buy PDF- 21pp US5659716  1997-08 Selvidge et al.  Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
Buy PDF- 18pp US5754827  1998-05 Barbier et al.  Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
Buy PDF- 16pp US5761484  1998-06 Agarwal et al.  Massachusetts Institute of Technology Virtual interconnections for reconfigurable logic systems
Buy PDF- 16pp US5777489  1998-07 Barbier et al.  Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
Buy PDF- 17pp US5790832  1998-08 Barbier et al.  Mentor Graphics Corporation Method and apparatus for tracing any node of an emulation
       
Foreign References: None

Other Abstract Info: DERABS C2003-800031

Other References:
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  • Shoup, "Programmable Cellular Logic," Xerox Corp., Palo Alto Research Center, Palo Alto, CA, undated, pp. 27-28, No Date.
  • Agarwal, "Virtual Wires: A Technology for Massive Multi-FPGA Systems," Virtual Machine Works, Inc., undated, pp. 1-24, No date.
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  • Kautz, et al., "Cellular Interconnection Arrays," IEEE Transactions on Computers, vol. C-17, No. 5, May 1968, pp. 443-451. Cited by 4 patents
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  • Sami, et al., "Reconfigurable Architectures for VLSI Processing Arrays," AFIPS Conference Proceedings, 1983 National Computer Conference, May 16-19, 1983, pp. 565-577. Cited by 24 patents
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  • Agrawal, et al., "A Hardware Logic Simulation System," IEEE Transactions on Computer-Aided Designs, vol. 9, No. 1, Jan. 1990, pp. 19-29. (11 pages) Cited by 4 patents
  • Babb, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulations," Masters Thesis, MIT, Department of EEC, Nov. 15, 1993, pp. 142-151; Also available as MIT/LCS Technical Report TR-586.
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  • Tessier, et al., "The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment," FPGA 1994, 2nd International ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Feb. 13-15, 1994.
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  • Bauer, "The Design of an Efficient Hardware Subroutine Protocol for FPGAs," Masters Thesis, MIT, Deparment of EEC, May 16, 1994, pp. 1-55; Also available as MIT/LCS Technical Report.
  • Jones, "A Time-Multiplexed FPGA Architecture for Logic Emulation," Masters Thesis, University of Toronto, Department of EEC, 1995, pp. 1-103.
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  • Pak K. Chan, et al.; Architectural Tradeoffs in Field-Programmable-Device-Based Computing Systems, IEEE 1993; pp. 152-161.


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