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 Title: |
US6631510:
Automatic generation of programmable logic device architectures
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Betz, Vaughn; Toronto, Canada
Rose, Jonathan; Toronto, Canada
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| Assignee: |
Altera Toronto Co., Nova Scotia, Canada
other patents from ALTERA TORONTO CO. (821196) (approx. 1)
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| Published / Filed: |
2003-10-07
/ 1999-10-29
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| Application Number: |
US1999000429013
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| IPC Code: |
Advanced:
G06F 17/50;
Core:
more...
IPC-7:
G06F 17/50;
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| ECLA Code: |
G06F17/50D4;
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| U.S. Class: |
716/016;
326/039;
326/041;
716/002;
716/004;
716/006;
716/012;
716/014;
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| Field of Search: |
716/002,4,6,11,12,14,16
326/039,41
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| Priority Number: |
| 1999-10-29 |
US1999000429013 |
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| Abstract: |
The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of different architectures. The Architecture Generation Engine converts a high-level, easily specified description of a PLD architecture into the highly detailed, complete PLD architecture database required by the internals of the CAD toolset in order to map a circuit netlist into the PLD. The Architecture Generation Engine also enables the performance evaluation of a wide variety of PLD architectures for given benchmark circuits.
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| Attorney, Agent or Firm: |
Fish & Neave ;
Tuma, Garry J. ;
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| Primary / Asst. Examiners: |
Siek, Vuthe; Do, Thuan
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| INPADOC Legal Status: |
None
Family Legal Status Report
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| Family: |
Show 2 known family members
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First Claim:
Show all 26 claims |
The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A method for generating an architecture for a programmable logic device (PLD), said method comprising the steps of:
- (a) creating a data file defining a high-level architecture description of the programmable logic device;
- (b) creating unique functional elements of the PLD generally matching the description in the said data file;
- (c) replicating and stitching together the functional elements to create a complete PLD architecture; and
- (d) generating a detailed description from the complete PLD architecture, for use by a CAD toolset.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
Show drawing descriptions
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| Description: |
Show description
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
S. Brown et al., "A Detailed Router For FIeld-Programmable Gate Arrays", IEEE Trans. on CAD, May 1992, pp. 620-628.
G. Lemieux et al., "A Detailed Router FOr Allocating Wire Segments In FPGAs," ACM/SIGDA Physical Design Workshop, 1993, p. 215-226.
D. Cronquist et al., "Emerald--An Architecture-Driven Tool Compiler for FPGAs", ACM Symp. on FPGAs, 1996, pp. 144-150.
P. Chow et al., The Design Of An SRAM-Based Field Programmable Gate Array, Part I: Architecture, Jun. 1999, pp. 191-197.
(7 pages)
Cited by 3 patents
[ISI abstract]
Ebeling et al., "Placement and Routhing Tools For The Triptych FPGA," IEEE Trans. on VLSI, Dec. 1995, pp. 473-482.
(10 pages)
Cited by 3 patents
[ISI abstract]
G. Lemieux et al., "On Two-Step Routing For FPGAs", ACM Symp. on Physical Design, 1997, pp. 60-66.
H. Hseih et al., "Third_Generation Architecture Boosts Speed And Density of Field-Programmable Gate Arrays", CICC, 1990, pp. 33.2.1-31.27.
M. Khellah et al., "Minimizing Interconnection Delays In Array-Based FPGAs," CICC, 1194, pp. 181-184.
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| Continuity Data: |
| Application Number | Filed | Notes |
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US2003000641193 | | is a
continuation of |
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>US1999000429013<
| 1999-10-29 |
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US6631510 issued 2003-10-07 Automatic generation of programmable logic device architectures
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