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Title: US7367024: Compiler-driven dynamic memory allocation methodology for scratch-pad based embedded systems
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Country: US United States of America

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16 pages

 
Inventor: Barua, Rajeev Kumar; Rockville, MD, United States of America
Udayakumaran, Sumesh; Hyattsville, MD, United States of America

Assignee: University of Maryland, Riverdale, MD, United States of America
other patents from UNIVERSITY OF MARYLAND (599690) (approx. 282)
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Published / Filed: 2008-04-29 / 2004-09-21

Application Number: US2004000945651

IPC Code: Advanced: G06F 9/45;
Core: more...

ECLA Code: G06F9/50A2M;

U.S. Class: 717/157; 717/153; 717/158; 717/160;

Field of Search: 717/140,164

Government Interest: STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
    This invention was made with government support under NSF contract no. CNS-0133519 awarded by the National Science Foundation. The government has certain rights in this invention.

Priority Number:
2004-09-21  US2004000945651

Abstract:     A highly predictable, low overhead and yet dynamic, memory allocation methodology for embedded systems with scratch-pad memory is presented. The dynamic memory allocation methodology for global and stack data (i) accounts for changing program requirements at runtime; (ii) has no software-caching tags; (iii) requires no run-time checks; (iv) has extremely low overheads; and (v) yields 100% predictable memory access times. The methodology provides that for data that is about to be accessed frequently is copied into the SRAM using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary.

Attorney, Agent or Firm: Carter, DeLuca, Farrell & Schmidt, LLP ;

Primary / Asst. Examiners: Dam, Tuan; Tecklu, Isaac T

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First Claim:
Show all 36 claims
    1. A method for dynamic memory allocation in a scratch-pad based embedded system, said method comprising the steps of:

partitioning an application program stored within the scratch-pad based embedded system into a plurality of regions;

representing the plurality of regions with a data structure having a plurality of nodes defining the regions, wherein each node represents one of a procedure, loop and variable of the application program;

assigning a timestamp to a starting point of each procedure and loop node of the plurality of nodes to form a timestamp order, the timestamp associated with each node of the data structure representing time order of execution during program execution;

determining a sequence of memory transfers at the starting point of each procedure and loop node between one type of memory and a scratch-pad memory of the embedded system in accordance with the timestamp order associated with the data structure, wherein the starting point of each procedure and loop node is a program point of the application program; and

performing memory transfers between the one type of memory and the scratch-pad memory at at least one program point of the application program during runtime according to the timestamp order.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (2)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 8pp US6108797  2000-08 Lin et al.  Winbond Electronics Corp. Method and system for loading microprograms in partially defective memory
Buy PDF- 25pp US6970985  2005-11 Moritz  Bluerisc Inc. Statically speculative memory accessing
       
Foreign References: None

Other References:
  • M. Kandemir “Dynamic Management of Scratch-Pad Memory Space”, ACM . . . , Jun. 18, 2001, pp. 690-695.
  • Manish Verma, Lars Wehmeyer, Peter Marwedel; Dynamic Overlay of Schratchpad Memory for Energy Minimization; pp. 104-109; Department of Computer Science XII; University of Dortmund, 44225 Dortmund, Germany, published in CODES+ISSS'04, Sep. 8-10, 2004, Stockholm, Sweden.
  • Ramanujam et al. “Dynamic Management of Scratch-Pad Memory Space”; pp. 690-695.
  • Moritz et al., “FlexCache: A Framework for Flexible Compiler Generated Data Caching”, thirteen pages.
  • Avissar et al., “An Optimal Memory Allocation Scheme for Scatch-Pad-Based Embedded Systems”, pp. 6-28.
  • Hallnor et al., A Fully Associative Software-Managed Cache Design, pp. 107-116.
  • Banakar et al., “Scratchpad Memory: A Design Alternative for Cache On-Chip Memory in Embedded Systems”, 6 pages.


  • Continuity Data:
    Application Number Filed Notes

    US2004000945651 2004-09-21  is a related to the prior publication
         US20060080372A1 issued 2006-04-13  Compiler-driven dynamic memory allocation methodology for scratch-pad based embedded systems


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