 |
|
|
|
|
|
 Title: |
US4701844:
Dual cache for independent prefetch and execution units
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Thompson, Richard F.; Santa Clara, CA
Disney, Daniel J.; Felton, CA
Quek, Swee-meng; San Jose, CA
Westerfeld, Eric C.; Milpitis, CA
|
| Assignee: |
Motorola Computer Systems, Inc., Cupertino, CA
other patents from MOTOROLA COMPUTER SYSTEMS, INC. (386725) (approx. 12)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1987-10-20
/ 1986-10-16
|
| Application Number: |
US1986000918667
|
| IPC Code: |
Advanced:
G06F 9/38;
G06F 12/08;
IPC-7:
G06F 9/00;
|
| ECLA Code: |
G06F9/38B6; G06F9/38D; G06F12/08B6M2;
|
| U.S. Class: |
Current:
711/119;
711/126;
711/E12.046;
712/E09.046;
712/E09.059;
Original:
364/200;
|
| Field of Search: |
364/200 MS File,900 MS File
|
| Priority Number: |
| 1986-10-16 |
US1986000918667 |
| 1984-03-30 |
US1984000595176 |
|
| Abstract: |
A pipelined digital computer processor system (10, FIG. 1) is provided comprising an instruction prefetch unit (IPU,2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, FIG. 3) for storing frequently accessed data, and a tag store (82, 92, FIG. 3) for indicating which main memory locations are contained in the respective cache. The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache permitting the use of self-modifying code. The IPU does not write to either cache. Provision is made for clearing the caches on certain conditions when their contents become invalid.
|
| Attorney, Agent or Firm: |
Nielsen, Walter W. ;
|
| Primary / Asst. Examiners: |
Harkcom, Gary V.; Lynt, C. H.
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
|
|
|
|
|
|
| Parent Case: |
This application is a continuation of application Ser. No. 595,176, filed 3/30/84, now abandoned.
|
| Designated Country: |
DE FR GB NL
|
| Family: |
Show 4 known family members
|
| Claim |
What is claimed is:
1. A digital computing system comprising:
- a main memory unit for storing at addressable locations thereof blocks of information, including instructions and operands, useable in said system; and
- a central processing unit for fetching and executing instructions comprising:
- an instruction prefetch unit for fetching said instructions;
- an arithmetic logic processing unit for executing said instructions;
- an instruction cache memory unit for storing blocks of said information, said instruction cache memory unit including first means coupled to said instruction prefetch unit for determining whether an instruction sought by said instruction prefetch unit is contained in said instruction cache memory unit, said first means also being coupled to said arithmetic logic processing unit for generating a first signal if information to be written by said arithmetic logic processing unit into said main memory unit is contained in said instruction cache memory unit; and
- an operand cache memory unit for storing blocks of said information, said operand cache memory unit including second means coupled to said arithmetic logic processing unit for determining whether an operand sought by said arithmetic logic processing unit is contained in said operand cache memory unit, said second means also being coupled to said arithmetic logic processing unit for generating a second signal if information to by written by said arithmetic logic processing unit into said main memory unit is contained in said operand cache memory unit;
- means enabling said arithmetic logic processing unit to write information simultaneously into said main memory unit and into said instruction cache memory unit in response to said first signal; and
- means enabling said arithmetic logic processing unit to write information simultaneously into said main memory and into said operand cache memory unit in response to said second signal.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 58 U.S. patent(s) that reference this one
|
|
