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Title: US5545915: Semiconductor device having field limiting ring and a process therefor
[ Derwent Title ]


Country: US United States of America

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9 pages

 
Inventor: Disney, Donald R.; Kokomo, IN
Sozansky, Wayne A.; Greentown, IN
Himelick, James M.; Kokomo, IN

Assignee: Delco Electronics Corporation, Kokomo, IN
other patents from DELCO ELECTRONICS CORPORATION (140125) (approx. 755)
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Published / Filed: 1996-08-13 / 1995-01-23

Application Number: US1995000376566

IPC Code: Advanced: H01L 23/58; H01L 29/06; H01L 29/10; H01L 29/78;
IPC-7: H01L 23/58; H01L 29/76; H01L 29/94;

ECLA Code: H01L29/78B2; H01L23/58B; H01L29/06D3B; H01L29/10G; T01L29/417D10;

U.S. Class: Current: 257/491; 257/339; 257/341; 257/490; 257/494; 257/E29.027; 257/E29.066; 257/E29.259;
Original: 257/491; 257/339; 257/341; 257/490; 257/494;

Field of Search: 257/335,337,339,341,342,488,490,491,494,495 437/041

Priority Number:
1995-01-23  US1995000376566

Abstract: A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells. The field limiting cells also contribute to forward current conduction when the device is in the on-state, thereby lowering the on-resistance of the device.

Attorney, Agent or Firm: Funke, Jimmy L. ;

Primary / Asst. Examiners: Loke, Steven H.;

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First Claim:
Show all 13 claims
The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:     1. A semiconductor device comprising:
  • a substrate;
  • a dielectric layer on a surface of the substrate;
  • a polysilicon layer on the dielectric layer so as to be electrically isolated from the substrate;
  • a first plurality of cells within an interior region of the surface of the semiconductor device, each of the first plurality of cells comprising a transistor having a source, a gate electrode formed by the polysilicon layer, and a drain formed by the substrate;
  • a second plurality of cells aligned on the substrate so as to circumscribe the first plurality of cells, thereby segregating the interior region from an exterior region on the surface of the substrate, each of the second plurality of cells comprising:
  • an opening extending through the dielectric and polysilicon layers to the surface of the substrate, the polysilicon layer forming a bridge between each adjacent pair of openings so as to interconnect the interior region and the exterior region, each bridge having a width;
  • a well of a first dopant type in the substrate beneath the opening, the well having a depth as measured from the surface of the substrate, the well laterally extending beneath each adjacent bridge so as to merge with the well of each adjacent cell of the second plurality of cells, such that the wells of the second plurality of cells form a continuous field limiting ring in the substrate of the semiconductor device; and
  • an island of a second dopant type in the well;
  • a gate contact in the exterior region of the semiconductor device and electrically interconnected with the polysilicon layer; and
  • a metallization layer having portions projecting through the openings and into the island and well of each of the second plurality of cells, the metallization layer being in electrical contact with the island of each of the second plurality of cells, the metallization layer being electrically isolated from the polysilicon layer;
  • wherein the second plurality of cells contribute to the current conduction of the semiconductor device in the on-state.


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Forward References: Show 22 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (22)   |   Backward references (2)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Get PDF - 9pp US4853345  1989-08 Himelick  Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
Get PDF - 7pp US5381031  1995-01 Shibib  AT&T Corp. Semiconductor device with reduced high voltage termination area and high breakdown voltage
       
Foreign References:
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Publication Date IPC Code Assignee   Title
  JP60150674 1985-08       
  JP02119184 1990-05       
  JP04017372 1992-01       


Other Abstract Info: CHEMABS 125(16)210405M CHEMABS 125(16)210405M DERABS G1996-383778 DERABS G1996-383778 DERABS G1997-488870

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