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Title: US5951707: Method of partitioning CRC calculation for a low-cost ATM adapter
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Country: US United States of America

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13 pages

 
Inventor: Christensen, Kenneth Jussi; Tampa, FL
Polge, Steven Eric; Cary, NC
Roginsky, Allen Leonid; Durham, NC

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 1999-09-14 / 1997-06-27

Application Number: US1997000884540

IPC Code: Advanced: H03M 13/09; H04L 1/00;
Core: H03M 13/00; more...
IPC-7: H03M 13/00;

ECLA Code: H04L1/00B7E; H03M13/09; H04L1/00B5;

U.S. Class: Current: 714/752; 370/466; 714/757;
Original: 714/752; 371/037.6; 370/060.1;

Field of Search: 371/37.01,37.6,37.1 370/60.1

Priority Number:
1997-06-27  US1997000884540

Abstract:     Described is a method and apparatus which calculates Cyclic Redundant Check (CRC) for an entity from partial CRCs associated with segments of the entity. The entity includes a data packet segmented into a plurality of Asynchronous Transfer Mode (ATM) cells. The Packet CRC is calculated from the algorithm (A1C1+A2C2 . . . +ANCN)/P with Ai, i=1, . . . , N, representing a partial CRC associated with a particular ATM cell, Ci, i-1, . . . , N, representing a Fixed Remainder and P is the CRC generation polynomial. The Ci values are calculated and stored in a table. The partial CRCs (i.e., Ai's) are calculated by hardware generator and forwarded to a processor which selects the corresponding value of Ci from the table and generates the CRC for the frame.

Attorney, Agent or Firm: Cockburn, Joscelyn G. ;

Primary / Asst. Examiners: Grant, William; Marc, McDieunel

Maintenance Status: E1 Expired  Check current status

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 16 claims
We claim:     1. A method for use in a communications system comprising the steps of:
  • (a) receiving segments (Bi) of a packet (B), with i=1, 2, 3, . . . , n;
  • (b) for each of the segments received, calculating a partial CRCi (i=1, 2, . . . n);
  • (c) storing each partial CRCi in a computer storage;
    • (c1) providing a table of Remainders with each Remainder having a predetermined relationship with each partial CRCi ;
  • (d) using a computer to access the computer storage and the table; and
  • (e) combining partial CRC's from the computer storage with related Remainders from the table to form the packet CRC's.


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Forward References: Show 26 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (26)   |   Backward references (15)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 16pp US3872430  1975-03 Boudreau et al.   Method and apparatus of error detection for variable length words using a polynomial code
Buy PDF- 12pp US4593393  1986-06 Mead et al.  Motorola, Inc. Quasi parallel cyclic redundancy checker
Buy PDF- 29pp US4712215  1987-12 Joshi et al.  Advanced Micro Devices, Inc. CRC calculation machine for separate calculation of checkbits for the header packet and data packet
Buy PDF- 27pp US4723243  1988-02 Joshi et al.  Advanced Micro Devices, Inc. CRC calculation machine with variable bit boundary
Buy PDF- 7pp US5251215  1993-10 Dravida et al.  AT&T Bell Laboratories Modifying check codes in data packet transmission
Buy PDF- 21pp US5280476  1994-01 Kojima et al.  Kabushiki Kaisha Toshiba Communication control system using an asynchronous transfer mode network
Buy PDF- 59pp US5282215  1994-01 Hyodo et al.  Fujitsu Limited Synchronization circuit
Buy PDF- 33pp US5313454  1994-05 Bustini et al.  Stratacom, Inc. Congestion control for cell networks
Buy PDF- 7pp US5325372  1994-06 Ish-Shalom  National Semiconductor Corporation Implementation of the HDLC CRC calculation
Buy PDF- 45pp US5379297  1995-01 Glover et al.  Network Equipment Technologies, Inc. Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode
Buy PDF- 22pp US5410546  1995-04 Boyer et al.  Storage Technology Corporation Apparatus and method for CRC computation over fixed length blocks containing variable length packets of data received out of order
Buy PDF- 7pp US5450399  1995-09 Sugita  NEC Corporation Clad having majority decision address table controller
Buy PDF- 14pp US5452330  1995-09 Goldstein  Digital Equipment Corporation Bus-oriented switching system for asynchronous transfer mode
Buy PDF- 47pp US5790842  1998-08 Charles et al.  Divicom, Inc. Processing system with simultaneous utilization of multiple clock signals
Buy PDF- 46pp US5793427  1998-08 Mills et al.  Divicom Inc. Processing system with delta-based video data encoding
       
Foreign References: None

Other Abstract Info: DERABS G1999-526976 DERABS G1999-526976

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