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Title: US6883070: Bandwidth-adaptive, hybrid, cache-coherence protocol
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Country: US United States of America

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10 pages

 
Inventor: Martin, Milo M. K.; Madison, WI, United States of America
Sorin, Daniel J.; Madison, WI, United States of America
Hill, Mark D.; Madison, WI, United States of America
Wood, David A; Madison, WI, United States of America

Assignee: Wisconsin Alumni Research Foundation, Madison, WI, United States of America
other patents from WISCONSIN ALUMNI RESEARCH FOUNDATION (631280) (approx. 1,178)
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Published / Filed: 2005-04-19 / 2001-10-19

Application Number: US2001000037727

IPC Code: Advanced: G06F 12/08;
Core: more...
IPC-7: G06F 12/08; G06F 15/167;

ECLA Code: G06F12/08B4P;

U.S. Class: 711/141; 711/146; 711/207; 709/224; 709/230;

Field of Search: 711/141,144-146,3,205,207 710/104-105,240 709/213,216,253,230,245,224,239,225

Government Interest: STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
    This invention was made with United States government support awarded by the following agencies:
    NSF 9971256
    The United States has certain rights in this invention.

Priority Number:
2001-10-19  US2001000037727
2001-03-14  US2001000275743P

Abstract:     A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which then identifies potential candidates to receive that message. The switching is according to the activity on the communication network used by the cache coherence messages. When network activity is high, a directory protocol is used to conserve bandwidth but when network activity is low, a snooping system is used to provide faster response.

Attorney, Agent or Firm: Quarles & Brady LLP ;

Primary / Asst. Examiners: Tran, Denise;

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Parent Case: CROSS-REFERENCE TO RELATED APPLICATIONS
    This application claims the benefit of provisional application No. 60/275,743 filed Mar. 14, 2001.

Family: Show 3 known family members

First Claim:
Show all 32 claims
    1. A method of coordinating at least two processor units, each having a processor and cache memory, and communicating cache coherence messages with each other and a shared memory over a network, the method comprising the steps of:

(a) providing a mechanism for communications of cache coherence messages directly from a given processor unit to another processor unit;

(b) providing a mechanism for communication of cache coherence messages directly from a given processor unit to a directory and then to at least one other processor unit when indicated by the directory;

(c) evaluating the available bandwidth on the network used to communicate the cache coherence messages; and

(d) for a given cache coherence message, selecting one the mechanism of step (a) or the mechanism of step (b) based on the evaluation of step (c).



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Forward References: Show 6 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (6)   |   Backward references (3)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 30pp US6510496  2003-01 Tarui et al.  Hitachi, Ltd. Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions
Buy PDF- 13pp US6535957  2003-03 Arimilli et al.  International Business Machines Corporation System bus read data transfers with bus utilization based data ordering
Buy PDF- 17pp US20010013089A1  2001-08 Weber   CACHE COHERENCE UNIT FOR INTERCONNECTING MULTIPROCESSOR NODES HAVING PIPELINED SNOOPY PROTOCOL
       
Foreign References: None

Other Abstract Info: DERABS C2003-057730

Other References:
  • Scott et al., “Performance of Pruning-Cache directories for large-Scale Multiprocessors” 1993, IEEE, vol. 4, No. 5, pp 520-534.* (15 pages) Cited by 11 patents [ISI abstract]
  • Bilir, E. Ender et al., Multicast Snooping: A New Coherence Method Using a Multicast Address Network, ISCA'99 Submission, University of Wisconsin—Madison, pp. 1-22, May 2-4, 1999.


  • Continuity Data:
    Application Number Filed Notes

    US2001000037727 2001-10-19  is a related to the prior publication
         US20020133674A1 issued 2002-09-19  Bandwidth-adaptive, hybrid, cache-coherence protocol

    US2001000037727 2001-10-19  is a non-provisional of provisional
    US2001000275743P  2001-03-14

    US2005000063294 2005-02-22  is a division of
    >US2001000037727<  2001-10-19   (granted)
         US6883070 issued 2005-04-19   Bandwidth-adaptive, hybrid, cache-coherence protocol


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