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 Title: |
US6981097:
Token based cache-coherence protocol
[ Derwent Title ]
>> View Certificate of Correction for this publication
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| Country: |
US United States of America
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| Inventor: |
Martin, Milo M. K.; Madison, WI, United States of America
Hill, Mark Donald; Madison, WI, United States of America
Wood, David Allen; Madison, WI, United States of America
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| Assignee: |
Wisconsin Alumni Research Foundation, Madison, WI, United States of America
other patents from WISCONSIN ALUMNI RESEARCH FOUNDATION (631280) (approx. 1,178)
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| Published / Filed: |
2005-12-27
/ 2003-03-14
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| Application Number: |
US2003000389861
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| IPC Code: |
Advanced:
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/00;
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| ECLA Code: |
G06F12/08B4P; G06F12/08B4P2E;
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| U.S. Class: |
711/130;
711/141;
711/142;
711/143;
711/144;
711/145;
707/008;
707/201;
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| Field of Search: |
707/008,201
709/216
711/141-145,130
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| Government Interest: |
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
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| Priority Number: |
| 2003-03-14 |
US2003000389861 |
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| Abstract: |
A cache coherence mechanism for a shared memory computer architecture employs tokens to designate a particular node's rights with respect to writing or reading a block of shared memory. The token system provides a correctness substrate to which a number of performance protocols may be freely added.
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| Attorney, Agent or Firm: |
Quarles & Brady LLP ;
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| Primary / Asst. Examiners: |
Nguyen, T;
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| Maintenance Status: |
CC Certificate of Correction issued
View Certificate of Correction
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
CROSS-REFERENCE TO RELATED APPLICATIONS
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| Family: |
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First Claim:
Show all 36 claims |
1. A computer system comprising: a) at least two processor units each having at least one processor and at least one cache; b) a shared collection of data; c) a communication channel allowing communication between the processor units and the shared collection of data; d) cache management means operating to: i) establish a set of tokens; ii) allow a processor to write to at least a portion of the shared collection of data through its cache only if the processor has all the tokens for that portion; and iii) allow a processor to read from at least a portion of the shared collection of data through its cache only if the processor has at least one of the tokens for that portion.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 3 U.S. patent(s) that reference this one
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