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 Title: |
US5572477:
Video ram method for outputting serial data
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jung, Seong-Ook; Seoul, Republic of Korea
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| Assignee: |
Samsung Electronics Co., Ltd., Suwon, Republic of Korea
other patents from SAMSUNG ELECTRONICS CO., LTD. (491065) (approx. 12,932)
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| Published / Filed: |
1996-11-05
/ 1995-03-31
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| Application Number: |
US1995000415057
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| IPC Code: |
Advanced:
G11C 7/00;
G11C 7/10;
G11C 11/401;
G11C 11/407;
G11C 11/409;
G11C 11/42;
Core:
G11C 11/21;
more...
IPC-7:
G11C 7/00;
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| ECLA Code: |
G11C7/10R; G11C7/10T;
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| U.S. Class: |
Current:
365/221;
365/049.17;
365/189.02;
365/189.05;
365/203;
Original:
365/221;
365/189.02;
365/189.05;
365/203;
365/049;
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| Field of Search: |
365/221,189.02,230.02,230.04,230.05,233,239,240,203,189.05,49
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| Priority Number: |
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| Abstract: |
The present invention relates to a video RAM as a dual port memory, and more particularly to the video RAM which is adjustable to a high speed system clock and a serial data output method thereof. In accordance with the present invention, the video RAM having a data register which outputs a serial data in response to the input of the serial address which is synchronized with a serial clock, comprises a first data I/O line for transferring the data which is synchronized with the even serial address and then is outputted from the data register, and a second data I/O line for transferring the data which is synchronized with the odd serial address and then is outputted from the data register. The video RAM according to the present invention has independent serial data output paths respectively for even address and odd address, thus enabling the serial data to be outputted every period of the serial clock. Consequently, it is possible to reduce the operation cycle time of the video RAM and to transfer data to a CRT at a high speed. In addition, it is possible to reduce the time interval between respective periods of the system clock.
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| Attorney, Agent or Firm: |
Cushman Darby & Cushman, L.L.P. ;
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| Primary / Asst. Examiners: |
Nguyen, Tan T.;
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| INPADOC Legal Status: |
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| Family: |
Show 17 known family members
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First Claim:
Show all 12 claims |
What is claimed is:
1. A video RAM having a data register for outputting serial data in response to the input of a serial address which is synchronized with a serial clock, said video RAM comprising:
- a first data I/O line for transferring even serial data which is output from the data register;
- a first column gate for synchronizing the even serial data stored in said data register with an even serial address and then transferring said even serial data to said first data I/O line;
- a second data I/O line for transferring odd serial data which is output from the data register;
- a second column gate for synchronizing the odd serial data stored in said data register with an odd serial address and then transferring said odd serial data to said second data I/O line; and
- a multiplexer for multiplexing said even and odd serial data on said first and second data I/O lines in response to an input of a column address and then transferring said multiplexed data to an I/O sense amplifier, thereby selectively accessing said even and odd serial data on said first and second data I/O lines when said serial address is received.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 9 U.S. patent(s) that reference this one
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