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 Title: |
US4768196:
Programmable logic array
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jou, Jing-Yang; Scotch Plains, NJ
Rosebrugh, Christopher; Belmont, MA
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| Assignee: |
Silc Technologies, Inc., Burlington, MA
other patents from SILC TECHNOLOGIES, INC. (514005) (approx. 2)
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| Published / Filed: |
1988-08-30
/ 1986-10-28
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| Application Number: |
US1986000923984
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| IPC Code: |
Advanced:
G01R 31/28;
G01R 31/3185;
G06F 11/22;
H03K 19/177;
G06F 11/27;
Core:
more...
IPC-7:
G01R 31/02;
G01R 31/28;
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| U.S. Class: |
Current:
714/725;
714/732;
714/737;
Original:
371/025;
371/026;
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| Field of Search: |
324/73 R
371/021,25,26
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| Priority Number: |
| 1986-10-28 |
US1986000923984 |
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| Abstract: |
Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaulated sequentially. A multiple input signature register which uses XQ +1 as its characteristic polynomial is used to evaulate the test results, where Q is the number of outputs. The final signature can be further compressed into only one bit. Instead of only determining the probability of fault detection, in this scheme, the fault detection capability has been analyzed using both the stuck at fault and the contact fault model. It can be shown that all of these faults can be detected. Shorts between two adjacent lines can be detected by using NOR gates.
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| Attorney, Agent or Firm: |
Wolf, Greenfield & Sacks ;
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| Primary / Asst. Examiners: |
Eisenzopf, Reinhard J.; Burns, W.
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
EP JP
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| Family: |
Show 6 known family members
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First Claim:
Show all 4 claims |
What is claimed is:
1. A programmable logic array (PLA) having built-in self-testing capability (BIST), said BIST PLA being capable of operating in a normal mode and a test mode, said BIST PLA comprising:
- (a) a plurality of PLA input lines coupled with decoding circuits, said decoding circuits being coupled via a plurality of bit lines with an AND array, said AND array being coupled via a plurality of product lines with an OR array, said OR array being coupled with a plurality of OR array output lines, the aggregate of signals across said OR array output lines at an instant of time being an output signature;
- (b) control signal receiver means for receiving a plurality of control signals from an external source, said control signals including a normal mode signal, a test mode signal, and a clock signal;
- (c) bit-line test-pattern generation means coupled with said bit lines and said control signal receiver means and responsive to said control signals, for generating a first predetermined sequence of test patterns across said bit lines when in said test mode in synchronization with said clock signal;
- (d) product-line test-pattern generation means coupled with said product lines and said control signal receiver means and responsive to said control signals, for generating a second predetermined sequence of test patterns across said product lines when in said test mode in synchronization with said clock signal;
- (e) multiple output signature compression means coupled with said OR array output lines and said control signal receiver means and responsive to said control signals, for compressing the sequence of output signatures occurring in said test mode into a single-bit test result and for passing through unaltered any output signature occurring in said normal mode, said multiple output signature compression means having XQ +1 as its characteristic polynomial where Q is the number of said OR Array output lines and X is a dummy variable;
- (f) means coupled with said multiple output signature compression means for transmitting said single-bit test result to an external receiver; and
- (g) at least one PLA output line coupled with said multiple output signature compression means.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 54 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G88-133337
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| Other References: |
"Built-In Tests for VLSI Finite-State Machines", by Hua et al., Proceedings FTCS-14, 1/83.
"Testing PLAs using Multiple Parallel Signature Analyzers by Hassan et al., Proceedings FTCS-13, pp. 422-425, 11/83.
"Hardware Approach to Self-Testing of Large Programmable Logic Arrays", by Daehn et al., IEEE Trans. on Comp., vol. C-30, #11, 11/81, pp. 829-833.
(5 pages)
Cited by 2 patents
"Implementing a Built-In Self-Test PLA Design", by Treuer et al., IEEE Des. & Test of Computers, 4/85, pp. 37-48.
(12 pages)
Cited by 3 patents
"Circuit Synthesis for the Silc Silicon Compiler", by Rosebrugh et al., IEEE Custom Integ. Circ. Conf., pp. 384-388, 6/85.
"Platypus: A PLA Test Pattern Generation Tool", by Wei et al., IEEE 22nd Design Autom. Confer., paper 14.2, pp. 197-203, 6/85.
"Detection of Faults in Programmable Logic Arrays", by Smith, IEEE Trans. on Comp., vol. C-28, #11, 11/79, pp. 845-853.
(9 pages)
Cited by 2 patents
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