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Title: US4825102: MOS FET drive circuit providing protection against transient voltage breakdown
[ Derwent Title ]


Country: US United States of America

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17 pages

 
Inventor: Iwasawa, Toshiyuki; Tokyo, Japan
Miura, Masayoshi; Kawasaki, Japan

Assignee: Matsushita Electric Industrial Co., Ltd. Japan
other patents from MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (358975) (approx. 19,828)
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Published / Filed: 1989-04-25 / 1987-09-11

Application Number: US1987000095457

IPC Code: Advanced: H03K 19/00; H03K 19/003;
IPC-7: H03K 3/013; H03K 17/08; H03K 17/16; H03K 17/284;

ECLA Code: H03K19/00P4; H03K19/003C;

U.S. Class: Current: 327/546; 327/409; 327/594; 347/009; 361/111;
Original: 307/296.5; 307/443; 307/451; 307/558; 307/542;

Field of Search: 307/443,585,450,451,270,279,475,452,453,542,555,558,568,576,579,264,605,592,296.5,234

Priority Number:
1986-09-11  JP1986000214381
1986-11-12  JP1986000269054
1986-11-12  JP1986000269057

Abstract: A drive circuit suitable for producing a high voltage drive output signal has an output stage formed of a P-channel MOS FET (4) and an N-channel MOS FET (5) connected for push-pull operation. The circuit is configured such that even with a supply voltage applied to the output stage which is higher than the ON-state withstand voltage of the MOS FETs, this value of voltage is prevented from being applied to a MOS FET which is in the ON stage, i.e. by providing voltage-dropping resistors (R1, R2) connected between the drain electrodes of the MOS FETs (4, 5) or utilizing a circuit which prevents each MOS FET from entering the ON state until after the other MOS FET has entered the OFF state.

Attorney, Agent or Firm: Lowe, Price, LeBlanc, Becker & Shur ;

Primary / Asst. Examiners: Miller, Stanley D.; Bertelson, David R.

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Designated Country: DE FR GB 

Family: Show 5 known family members

First Claim:
Show all 22 claims
What is claimed is:     1. A drive circuit comprising a P-channel field effect transistor and an N-channel field effect transistor connected in a push-pull configuration, a first resistor having first and second terminals, said first terminal being connected to a drain electrode of said P-channel field effect transistor, said first resistor having a resistance value which is higher than an ON-state internal resistance value of said P-channel field effect transistor, a second resistor having first and second terminals, said first terminal of said second resistor being connected to a drain electrode of said N-channel field effect transistor, said second resistor having a resistance value which is higher than an ON-state internal resistance value of said N-channel field effect transistor, with the respective second terminals of said first and second resistors being mutually connected to form a junction which constitutes an output terminal of said drive circuit.

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Description: Show description

Forward References: Show 19 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (19)   |   Backward references (8)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Get PDF - 5pp US3651340  1972-03 Cliff  Hamilton Watch Company CURRENT LIMITING COMPLEMENTARY SYMMETRY MOS INVERTERS
Get PDF - 6pp US4103190  1978-07 Beutler  Motorola, Inc. Complementary power saving comparator/inverter circuits
Get PDF - 6pp US4164842  1979-08 Ebihara  Citizen Watch Co., Ltd. Buffer amplifier circuit
Get PDF - 11pp US4233525  1980-11 Takahashi et al.  Fujitsu Limited Electronic circuit for use in a digital circuit which prevents passage of pulses having a pulse width narrower than a predetermined value
Get PDF - 7pp US4467224  1984-08 Maddox  RCA Corporation System for applying a high voltage source to a CRT through a capacitive load
Get PDF - 9pp US4525635  1985-06 Gillberg  RCA Corporation Transient signal suppression circuit
Get PDF - 11pp US4540904  1985-09 Ennis et al.  The United States of America as represented by the Secretary of the Air Force Tri-state type driver circuit
Get PDF - 9pp US4620310  1986-10 Lvovsky  Metapath Inc. Method and apparatus for generating bipolar pulses in a local area network
       
Foreign References:
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Publication Date IPC Code Assignee   Title
  JP53086151 1978-07       
  JP54032259 1979-03       
  JP54142061 1979-11       
  JP56012128 1981-02       
  JP57063861 1982-04       
  JP58121829 1983-07       
  JP58142626 1983-08       


Other Abstract Info: DERABS G88-113852 JAPABS 120293E000062 JAPABS 120375E000013

Other References:
  • Electronic Design, 18th Apr. 1985, pp. 52, 53; D. Bursky: "CMOS ICs Handle High-Voltage Needs of RS-232 Interface".


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