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 Title: |
US4825102:
MOS FET drive circuit providing protection against transient voltage breakdown
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Iwasawa, Toshiyuki; Tokyo, Japan
Miura, Masayoshi; Kawasaki, Japan
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| Assignee: |
Matsushita Electric Industrial Co., Ltd. Japan
other patents from MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (358975) (approx. 19,828)
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| Published / Filed: |
1989-04-25
/ 1987-09-11
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| Application Number: |
US1987000095457
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| IPC Code: |
Advanced:
H03K 19/00;
H03K 19/003;
IPC-7:
H03K 3/013;
H03K 17/08;
H03K 17/16;
H03K 17/284;
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| ECLA Code: |
H03K19/00P4; H03K19/003C;
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| U.S. Class: |
Current:
327/546;
327/409;
327/594;
347/009;
361/111;
Original:
307/296.5;
307/443;
307/451;
307/558;
307/542;
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| Field of Search: |
307/443,585,450,451,270,279,475,452,453,542,555,558,568,576,579,264,605,592,296.5,234
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| Priority Number: |
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| Abstract: |
A drive circuit suitable for producing a high voltage drive output signal has an output stage formed of a P-channel MOS FET (4) and an N-channel MOS FET (5) connected for push-pull operation. The circuit is configured such that even with a supply voltage applied to the output stage which is higher than the ON-state withstand voltage of the MOS FETs, this value of voltage is prevented from being applied to a MOS FET which is in the ON stage, i.e. by providing voltage-dropping resistors (R1, R2) connected between the drain electrodes of the MOS FETs (4, 5) or utilizing a circuit which prevents each MOS FET from entering the ON state until after the other MOS FET has entered the OFF state.
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| Attorney, Agent or Firm: |
Lowe, Price, LeBlanc, Becker & Shur ;
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| Primary / Asst. Examiners: |
Miller, Stanley D.; Bertelson, David R.
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
DE FR GB
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| Family: |
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First Claim:
Show all 22 claims |
What is claimed is:
1. A drive circuit comprising a P-channel field effect transistor and an N-channel field effect transistor connected in a push-pull configuration, a first resistor having first and second terminals, said first terminal being connected to a drain electrode of said P-channel field effect transistor, said first resistor having a resistance value which is higher than an ON-state internal resistance value of said P-channel field effect transistor, a second resistor having first and second terminals, said first terminal of said second resistor being connected to a drain electrode of said N-channel field effect transistor, said second resistor having a resistance value which is higher than an ON-state internal resistance value of said N-channel field effect transistor, with the respective second terminals of said first and second resistors being mutually connected to form a junction which constitutes an output terminal of said drive circuit.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 19 U.S. patent(s) that reference this one
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