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 Title: |
US4891751:
Massively parallel vector processing computer
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Call, Duane B.; Provo, UT
Mudrow, Alfred; Orem, UT
Johnson, Randall C.; Orem, UT
Bennion, Robert F.; Provo, UT
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| Assignee: |
Floating Point Systems, Inc., Beaverton, OR
other patents from FLOATING POINT SYSTEMS, INC. (201195) (approx. 7)
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| Published / Filed: |
1990-01-02
/ 1987-03-27
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| Application Number: |
US1987000031697
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| IPC Code: |
Advanced:
G06F 15/173;
G06F 15/80;
Core:
G06F 15/16;
G06F 15/76;
IPC-7:
G06F 13/00;
G06F 15/16;
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| U.S. Class: |
Current:
712/006;
Original:
364/200;
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| Field of Search: |
364/200 MS File,900 MS File
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| Priority Number: |
| 1987-03-27 |
US1987000031697 |
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| Abstract: |
A massively parallel vector computer comprises a set of vector processing nodes, each node including a main processor for controlling access to a random access memory through an internal bus and a set of ports for interfacing external busses to the internal bus. The external busses interconnect pairs of nodes to form a network through which data may be transmitted from the random access memory in any one node to the random access memory in any other node in the network. Each vector processing node also includes a vector memory accessed through a local bus, the local and internal busses communicating via an additional port controlled by the main processor. A vector processor within each node performs operations on vectors stored in the vector memory and stores the results in the vector memory. A peripheral processing network comprises a set of peripheral processing nodes interconnected via further busses, and wherein selected peripheral processing nodes are coupled to selected vector processing nodes. The peripheral processing nodes are adapted to transmit data to and receive data from peripheral devices.
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| Attorney, Agent or Firm: |
Dellett, Smith-Hill & Bedell ;
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| Primary / Asst. Examiners: |
James, Andrew J.; Nguyen, Viet
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 13 claims |
We claim:
1. A vector processing node for a computer of the type having a network of simultaneously operating vector processing nodes interconnected by bidirectional external busses for conveying parallel data words between said vector processing nodes, the vector processing node comprising:
- a bi-directional first bus for conveying parallel data words;
- a bi-directional second bus for conveying parallel data words;
- vector memory means connected for read and write access through said second bus for storing vectors comprising sequences of parallel data words conveyed on said second bus;
- vector processing means connected to said second bus for transmitting parallel data words to and receiving parallel data words from said vector memory means for generating output vectors comprising functions of input vectors stored in said vector memory means and for storing said output vectors in said vector memory means; and
- control means including a computer processor connected to said first bus, external port means controlled by said computer processor and connected between said first bus and said external busses, and local port means controlled by said computer processor connected between said first and second busses, for transmitting parallel data words to and receiving parallel data words from said first bus, said second bus, said external busses, and said vector memory means for selectively transferring parallel data words from a selected one of said external busses to said first bus, from said first bus to a selected one of said external busses, between said first bus and said second bus, and between said second bus and said vector memory means.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 42 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
John P. Hayes, "A Microprocessor-based Hypercube Supercomputer", IEEE Micro, Oct. 1986, pp. 6-17.
(12 pages)
Cited by 35 patents
Robert Rosenberg, "Super Cube", Electronics Week, Feb./85, pp. 15-17.
(3 pages)
Paul Wiley, "A parallel architecture comes of age at last", IEEE Spectrum, Jun. 87, pp. 46-50.
(5 pages)
Ray Asbury, "Concurrent Computers Ideal for Inherently Parallel Problems", Computer Design, Sep./85, pp. 99-107.
Cited by 11 patents
Wesley R. Iversen, "New CMOS Chip Processes Data in Parallel", Electronics Week, Nov./84, pp. 17-18.
(2 pages)
Azriel Rosenfeld, "Parallel Image Processing Using Cellular Arrays", IEEE Computer, Jan./83, pp. 14-20.
(7 pages)
Cited by 6 patents
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