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 Title: |
US5148539:
Address bus control apparatus
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Enomoto, Hiromichi; Hadano, Japan
Kobayashi, Kazushi; Ebina, Japan
Jikihara, Masami; Yamato, Japan
Amako, Norihisa; Hadano, Japan
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| Assignee: |
Hitachi, Ltd., Tokyo, Japan
other patents from HITACHI, LTD (252865) (approx. 26,413)
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| Published / Filed: |
1992-09-15
/ 1991-06-04
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| Application Number: |
US1991000711254
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| IPC Code: |
Advanced:
G06F 13/40;
Core:
more...
IPC-7:
G06F 12/00;
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| U.S. Class: |
Current:
710/307;
Original:
395/425;
364/DIG.1;
364/240;
364/240.3;
364/245.6;
364/247;
364/242.2;
364/254.9;
364/255.1;
364/255.4;
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| Field of Search: |
364/200 MS File,900 MS File,240.3,DIG. 1,DIG. 2
395/400,425
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| Priority Number: |
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| Abstract: |
An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.
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| Attorney, Agent or Firm: |
Fay, Sharpe, Beall, Fagan, Minnich & McKee ;
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| Primary / Asst. Examiners: |
Fleming, Michael R.; Sheikh, Ayaz R.
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| Maintenance Status: |
E3 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This is a continuation of co-pending application Ser. No. 256,402 filed on Oct. 11, 1988, now abandoned.
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| Family: |
Show 14 known family members
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First Claim:
Show all 12 claims |
What is claimed is:
1. An address bus control apparatus for a data processing system having a first address bus, a second address bus with a width smaller than that of said first address bus, a processor and a memory unit connected with said first address bus, and a plurality of input/output units connected with said second address bus, at least one of said plurality of input/output units being an accessing unit which accesses said memory unit or another one of said input/output units by generating bus identifying information which identifies at least one of said address buses to which the accessed memory unit or another one of said input/output units is connected and generating address information whose width is not larger than the width of said second address bus, said address bus control apparatus comprising:
- signal receiving means connected with said accessing unit for receiving said bus identifying information;
- first storing means for storing first predetermined address information having a width corresponding to a predetermined difference between the address information width of said accessing unit and the width of said first address bus; and
- first address information transmitting means connected with said first and second address buses, said signal receiving means, and said first storing means and responsive to said bus identifying information for transmitting said first predetermined address information from said first storing means and the address information generated by said accessing unit from said second address bus, respectively, onto said first address bus when said bus identifying information identifies said first address bus.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 18 U.S. patent(s) that reference this one
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