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 Title: |
US5359566:
Dynamic random access memory
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Furuyama, Tohru; tokyo, Japan
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| Assignee: |
Kabushiki Kaisha Toshiba, Kawasaki, Japan
other patents from TOSHIBA CORPORATION (581270) (approx. 23,590)
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| Published / Filed: |
1994-10-25
/ 1992-05-29
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| Application Number: |
US1992000890252
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| IPC Code: |
Advanced:
G11C 11/404;
G11C 11/405;
H01L 21/8242;
H01L 27/10;
H01L 27/108;
Core:
G11C 11/403;
H01L 21/70;
more...
IPC-7:
G11C 11/24;
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| ECLA Code: |
G11C11/404;
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| U.S. Class: |
Current:
365/149;
365/189.12;
365/189.14;
365/189.16;
365/203;
365/205;
365/207;
365/221;
365/239;
Original:
365/149;
365/189.01;
365/189.12;
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| Field of Search: |
365/149,203,222,189.01,189.12,230.06,233,194
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| Priority Number: |
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| Abstract: |
A semiconductor memory device according this invention comprises a memory cell array in which cascade memory cells arranged in matrix form, each cell being composed of a plurality of MOS transistors cascade-connected to each other, and a plurality of information storing capacitors one end of each of which is connected to one end of each of the transistors, respectively, word lines equally connected to the memory cells in each row of the memory cell array, a bit line equally connected to each column of the memory cell array, a capacitor-plate line provided for each column of the memory cell array, and equally connected to the other end of each of the capacitor groups in the memory cells in the corresponding column, a bit-line precharger circuit connected to each of the bit lines, a capacitor-plate line precharger circuit connected to each of the capacitor-plate lines, and a sense amplifier circuit which is provided for column of the memory cell array, and which senses the potential between the bit line and the capacitor-plate line in the read operation.
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| Attorney, Agent or Firm: |
Banner, Birch, McKie & Beckett ;
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| Primary / Asst. Examiners: |
LaRoche, Eugene R.; Niranjan, F.
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Family: |
Show 5 known family members
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First Claim:
Show all 45 claims |
What is claimed is:
1. A semiconductor memory device comprising:
- a memory cell array in which cascade memory cells arranged in matrix form, each cell being composed of a plurality of MOS transistors cascade-connected to each other, and a plurality of information storing capacitors one end of each of which is connected to one end of each of the transistors, respectively;
- word lines equally connected to the memory cells in each row of the memory cell array;
- a bit line equally connected to each column of the memory cell array;
- a capacitor-plate line provided for each column of the memory cell array, and equally connected to the other end of each of the capacitor groups in said memory cells in the corresponding column;
- a bit-line precharger circuit connected to each of said bit lines;
- a capacitor-plate line precharger circuit connected to each of said capacitor-plate lines; and
- a sense amplifier circuit which is provided for column of said memory cell array, and which senses the potential between said bit line and said capacitor-plate line in the read operation.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 17 U.S. patent(s) that reference this one
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| Foreign References: |
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| Other Abstract Info: |
DERABS G93-023549
JAPABS 170215P000142
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| Other References: |
K. Kimura, et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture", ISSCC 91, pp. 106-107, Feb. 1991.
M. Asakura, et al., "Cell-Plate Line Connecting Complementary Bitline (C3) Architecture for Battery Operating DRAMS", 1991 Sym. on VLSICKTS, pp. 59-60, May 30, 1991.
Arimoto et al., "A Circuit Design of Intelligent CDRAM with Automatic Write back Capability", 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 79-80.
Shah et al., "A 4Mb DRAM with Cross-point Trench Transistor Cell", 1986 ISSCC Digest of Technical Papers, pp. 268-269.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", 1988 IEDM Technical Digest, pp. 592-595.
Watanabe et al., "Stacked Capacitor Cells for High-density Dynamic RAMs", 1988 IEDM Technical Digest, pp. 600-603.
Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256 MBit DRAMs", 1989 IEDM Technical Digest, pp. 23-26.
Fujishima et al., "A storage-Node-Boosted RAM with Word-Line Delay Compensation", IEEE Journal of Solid State Circuits, vol. SC-17, No. 5, pp. 872-875, Oct. 1982.
(5 pages)
Cited by 18 patents
Ohta et al., "A Novel Memory cell Architecture for High-Density DRAMs", 1989 Symposium of VLSI Circuits, Digest of Tech. Papers, pp. 101-102.
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta2 O5 High Density VLSI Dynamic Memory", IEEE Transactions on Electron Devices, vol. ED-29, No. 3, Mar. 1982, pp. 368-376.
(9 pages)
Cited by 19 patents
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