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 Title: |
US5381114:
Continuous time common mode feedback amplifier
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Pena-Finol, Jesus S.; Coral Springs, FL
Chambers, Mark J.; Plantation, FL
Phillips, James B.; Plantation, FL
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| Assignee: |
Motorola, Inc., Schaumburg, IL
other patents from MOTOROLA, INC. (386735) (approx. 18,357)
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| Published / Filed: |
1995-01-10
/ 1994-04-04
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| Application Number: |
US1994000223416
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| IPC Code: |
Advanced:
H03F 3/45;
Core:
more...
IPC-7:
H03F 3/45;
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| ECLA Code: |
H03F3/45S1B1B; H03F3/45S3B1A;
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| U.S. Class: |
Current:
330/258;
330/253;
330/257;
Original:
330/258;
330/253;
330/257;
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| Field of Search: |
330/253,257,258
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| Priority Number: |
| 1994-04-04 |
US1994000223416 |
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| Abstract: |
A continuous time common mode feedback amplifier CTCMFB (300) is suitable for applications requiring fully differential amplifiers in low voltage supply requirements. Two mirror image, low gain CMOS amplifiers (MP0/MP2 and MP3/MP4) in the CTCMFB (300) define and stabilize the common mode output voltage, Vcm, of the main differential amplifier (102). The transient response of the common mode amplifier (300) can be adjusted independently of the transient response of the main differential amplifier (102), allowing fast transient response to the main differential amplifier.
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| Attorney, Agent or Firm: |
Hernandez, Pedro P. ;
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| Primary / Asst. Examiners: |
Mullins, James B.;
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Family: |
Show 4 known family members
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First Claim:
Show all 13 claims |
What is claimed is:
1. A CMOS common mode differential amplifier having first and second supply nodes for receiving first and second supply voltages, first and second common mode inputs, and a reference input, comprising:
- first and second low gain FET amplifier circuits coupled in a mirror image configuration for providing first and second common mode currents;
- first and second bias FETs biased in saturation for biasing the first and second low gain FET amplifier circuits into their triode region;
- first and second cascode FETs operatively coupled to the first and second low gain FET amplifier circuits for controlling a response time of the CMOS common mode differential amplifier;
- a current mirror circuit for providing first and second current sources to bias the first and second bias FETs; and
- a current to voltage converter responsive to the first and second common mode currents for providing a control voltage output of the CMOS common mode differential amplifier.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 8 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G1995-060504
DERABS G1995-060504
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| Other References: |
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, "A Family of Differential NMOS Analog Circuits for a PCM Codec Filer Chip" pp. 1014-1023, Dec. 1982.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique" pp. 828-836, Dec. 1984.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, "A Pipelined 5-Msample/s 9-bit Analog-to-digital converter" pp. 954-960, Dec. 1987.
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, "A Pipelined 13-bit, 250-ks/s, 5-v Analog-to-digital Converter" pp. 1316-1323, Dec. 1988.
Gregorian R., and Temes G, Analog Mos integrated Circuit, New York: Wiley-Interscience, 1986, pp. 254-256.
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