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 Title: |
US5483691:
Zero intermediate frequency receiver having an automatic gain control circuit
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Heck, Joseph P.; Ft. Lauderdale, FL
Ferrer, Enrique; Miami, FL
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| Assignee: |
Motorola, Inc., Schaumburg, IL
other patents from MOTOROLA, INC. (386735) (approx. 18,357)
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| Published / Filed: |
1996-01-09
/ 1994-07-14
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| Application Number: |
US1994000275088
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| IPC Code: |
Advanced:
H03G 3/20;
H04B 1/10;
H04B 1/16;
IPC-7:
H04B 1/16;
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| ECLA Code: |
H03G3/30E3; H04B1/10S;
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| U.S. Class: |
Current:
455/234.2;
375/345;
455/209;
455/241.1;
455/245.2;
Original:
455/234.2;
455/209;
455/241.1;
455/245.2;
375/345;
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| Field of Search: |
455/234.1,234.2,236.1,239.1,241.1,251.1,253.2,245.1,245.2,315,324
330/278
375/345
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| Priority Number: |
| 1994-07-14 |
US1994000275088 |
| 1992-06-08 |
US1992000895309 |
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| Abstract: |
A receiver automatic gain control (AGC) circuit includes a first adjustable gain control amplifier (158) which is responsive to a gain control signal (156). The AGC circuit further includes a second adjustable gain control amplifier (114) and a control circuit (116) which receives the gain control signal (156) and provides a modified gain control signal or VCNTRL (152) to the second adjustable control amplifier (114). The control circuit (116) also limits the amount of gain control applied to adjustable gain control amplifiers (114 and 118) when the gain control signal (156) reaches a certain predetermined level. This provides for all further gain reduction to occur at the first adjustable gain control amplifier (158) and thereby reduce the chances for distortion under high input signal conditions.
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| Attorney, Agent or Firm: |
Hernandez, Pedro P. ;
Doutre, Barbara R. ;
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| Primary / Asst. Examiners: |
Urban, Edward F.;
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This is a continuation of application Ser. No. 07/895,309, filed Jun. 6, 1992 and now abandoned.
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| Designated Country: |
DE FR GB SE EP JP KR
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| Family: |
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First Claim:
Show all 8 claims |
What is claimed is:
1. A zero intermediate frequency (zero IF) receiver, comprising:
- a first adjustable gain stage having an input terminal for receiving an input signal, the first adjustable gain stage being responsive to a gain control signal for adjusting the amount of gain provided to the input signal and providing an amplified output signal at an output terminal;
- first and second down mixers coupled to the output terminal of the first adjustable gain stage and providing first and second phase-related baseband signals;
- a second adjustable gain stage for receiving the first and second phase-related baseband signals and providing first and second amplified baseband signals in response to a modified gain control signal;
- a control means coupled to the first and second adjustable gain stages and responsive to the gain control signal for providing the modified gain control signal to the second adjustable gain stage for adjusting the gain of the second adjustable gain stage depending on the level of the modified gain control signal, the control means including a limiting means for limiting the maximum amount of gain reduction applied to the second adjustable gain stage upon the gain control signal reaching a predetermined gain reduction limit threshold level, wherein the gain of the first adjustable gain stage is reduced prior to the gain of the second adjustable gain stage;
- first and second up mixers for converting the first and second amplified baseband signals into first and second amplified phase-related signals; and
- an adder for summing the first and second amplified phase-related signals to produce the gain control signal.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 142 U.S. patent(s) that reference this one
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