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Title: US6366121: Programmable logic array integrated circuit architectures
[ Derwent Title ]


Country: US United States of America

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27 pages

 
Inventor: Cliff, Richard G.; Milpitas, CA
Heile, Francis B.; Santa Clara, CA
Huang, Joseph; San Jose, CA
Lane, Christopher F.; Campbell, CA
Lee, Fung Fung; Milpitas, CA
McClintock, Cameron; Mountain View, CA
Mendel, David W.; Sunnyvale, CA
Ngo, Ninh D.; San Jose, CA
Pedersen, Bruce B.; San Jose, CA
Reddy, Srinivas T.; Fremont, CA
Sung, Chiakang; Milpitas, CA
Veenstra, Kerry; San Jose, CA
Wang, Bonnie I.; Cupertino, CA

Assignee: Altera Corporation, San Jose, CA
other patents from ALTERA CORPORATION (21885) (approx. 622)
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Published / Filed: 2002-04-02 / 2001-05-25

Application Number: US2001000865227

IPC Code: Advanced: H03K 19/173; H03K 19/177;
Core: more...
IPC-7: G06F 7/38; H03K 19/177;

ECLA Code: H03K19/173C2; H03K19/177;

U.S. Class: 326/041; 326/039;

Field of Search: 326/041,38,39

Priority Number:
2001-05-25  US2001000865227
1999-06-09  US1999000328704
1997-02-28  US1997000807561
1995-05-17  US1995000442795
1996-07-10  US1996000021449P

Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

Attorney, Agent or Firm: Fish & Neave ; Jackson, Robert R. ;

Primary / Asst. Examiners: Tokar, Michael; Chang, David D.

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

       
Related Applications:
Application Number Filed Patent Pub. Date  Title
US1999000328704 1999-06-09       
US1997000807561 1997-02-28    1999-10-05  Programmable logic array integrated circuit architectures
US1995000442795 1995-05-17    1997-11-18  Programmable logic array integrated circuit devices


       
Parent Case:

CROSS REFERENCE TO RELATED APPLICATIONS
    This is a continuation of U.S. patent application Ser. No. 09/328,704, filed Jun. 9, 1999, which is a division of U.S. patent application Ser. No. 08/807,561, filed Feb. 28, 1997 (now U.S. Pat. No. 5,963,049), which is a continuation-in-part of U.S. patent application Ser. No. 08/442,795, filed May 17, 1995 (now U.S. Pat. No. 5,689,195) and which claims the benefit of U.S. provisional patent application No. 60/021,449, filed Jul. 10, 1996. All of these prior applications are hereby incorporated by reference herein in their entireties.

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First Claim:
Show all 16 claims
The invention claimed is:     1. A programmable logic device comprising:
  • a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, each of the regions including a plurality of subregions of programmable logic;
  • a plurality of interconnection conductors extending parallel to each of the rows;
  • driver circuitry associated with each of the interconnection conductors and adapted to drive an applied signal onto the associated interconnection conductor; and
  • selection circuitry associated with each driver circuitry and adapted to select an output signal of any one of at least three of the subregions that are respectively located in three of the columns that are adjacent to one another as the signal applied to the associated driver circuitry.


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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (39)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
  US3473160  1969-10 Wahlstrom   ELECTRONICALLY CONTROLLED MICROELECTRONIC CELLULAR LOGIC ARRAY
Buy PDF- 11pp US4609986  1986-09 Hartmann et al.  Altera Corporation Programmable logic array device using EPROM technology
Buy PDF- 25pp US4617479  1986-10 Hartmann et al.  Altera Corporation Programmable logic array device using EPROM technology
Buy PDF- 22pp US4642487  1987-02 Carter  Xilinx, Inc. Special interconnect for configurable logic array
Buy PDF- 14pp US4677318  1987-06 Veenstra  Altera Corporation Programmable logic storage element for programmable logic devices
Buy PDF- 10pp US4713792  1987-12 Hartmann et al.  Altera Corporation Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits
Buy PDF- 22pp US4758745  1988-07 Elgamel et al.  Actel Corporation User programmable integrated circuit interconnect architecture and test method
Buy PDF- 25pp US4774421  1988-09 Hartmann et al.  Altera Corporation Programmable logic array device using EPROM technology
Buy PDF- 22pp US4871930  1989-10 Wong et al.  Altera Corporation Programmable logic device with array blocks connected via programmable interconnect
Buy PDF- 18pp US4899067  1990-02 So et al.  Altera Corporation Programmable logic devices with spare circuits for use in replacing defective circuits
Buy PDF- 21pp US4912342  1990-03 Wong et al.  Altera Corporation Programmable logic device with array blocks with programmable clocking
Buy PDF- 8pp US5023606  1991-06 Kaplinsky  Plus Logic, Inc. Programmable logic device with ganged output pins
Buy PDF- 7pp US5073729  1991-12 Greene et al.  Actel Corporation Segmented routing architecture
Buy PDF- 5pp US5121006  1992-06 Pedersen  Altera Corporation Registered logic macrocell with product term allocation and adjacent product term stealing
Buy PDF- 18pp US5122685  1992-06 Chan et al.  QuickLogic Corporation Programmable application specific integrated circuit and logic cell therefor
Buy PDF- 8pp US5132571  1992-07 McCollum et al.  Actel Corporation Programmable interconnect architecture having interconnects disposed above function modules
Buy PDF- 18pp US5144166  1992-09 Camarota et al.  Concurrent Logic, Inc. Programmable logic cell and array
Buy PDF- 19pp US5208491  1993-05 Ebeling et al.  Washington Research Foundation Field programmable gate array
Buy PDF- 5pp US5220214  1993-06 Pedersen  Altera Corporation Registered logic macrocell with product term allocation and adjacent product term stealing
Buy PDF- 9pp US5258668  1993-11 Cliff et al.  Altera Corporation Programmable logic array integrated circuits with cascade connections between logic modules
Buy PDF- 16pp US5260610  1993-11 Pedersen et al.  Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
Buy PDF- 20pp US5260611  1993-11 Cliff et al.  Altera Corporation Programmable logic array having local and long distance conductors
Buy PDF- 8pp US5274581  1993-12 Cliff et al.  Altera Corporation Look up table implementation of fast carry for adders and counters
Buy PDF- 10pp US5350954  1994-09 Patel  Altera Corporation Macrocell with flexible product term allocation
Buy PDF- 19pp US5371422  1994-12 Patel et al.  Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
Buy PDF- 14pp US5448186  1995-09 Kawata  Fuji Xerox Co., Ltd. Field-programmable gate array
Buy PDF- 22pp US5457410  1995-10 Ting  BTR, Inc. Architecture and interconnect scheme for programmable logic circuits
Buy PDF- 66pp US5469003  1995-11 Kean  Xilinx, Inc. Hierarchically connectable configurable cellular array
Buy PDF- 8pp US5483178  1996-01 Costello et al.  Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
Buy PDF- 16pp US5509128  1996-04 Chan  Actel Corporation FPGA architecture including direct logic function circuit to I/O interconnections
Buy PDF- 14pp US5543732  1996-08 McClintock et al.  Altera Corporation Programmable logic array devices with interconnect lines of various lengths
Buy PDF- 10pp US5565793  1996-10 Pedersen  Altera Corporation Programmable logic array integrated circuit devices with regions of enhanced interconnectivity
Buy PDF- 37pp US5670895  1997-09 Kazarian et al.  Altera Corporation Routing connections for programmable logic array integrated circuits
Buy PDF- 25pp US5689195  1997-11 Cliff et al.  Altera Corporation Programmable logic array integrated circuit devices
Buy PDF- 9pp US5705939  1998-01 McClintock et al.  Altera Corporation Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors
Buy PDF- 22pp US5764080  1998-06 Huang et al.  Altera Corporation Input/output interface circuitry for programmable logic array integrated circuit devices
Buy PDF- 8pp US5872463  1999-02 Pedersen  Altera Corporation Routing in programmable logic devices using shared distributed programmable logic connectors
Buy PDF- 18pp US5909126  1999-06 Cliff et al.  Altera Corporation Programmable logic array integrated circuit devices with interleaved logic array blocks
Buy PDF- 30pp USRE34363  1993-08 Freeman  Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
       
Foreign References:
Buy
PDF
Publication Date IPC Code Assignee   Title
Buy PDF- 69pp EP0461798 1991-12  H03K 19/177 ADVANCED MICRO DEVICES, INC. Configurable interconnect structure 
Buy PDF- 23pp GB2283602 1995-05  H03K 19/177 ALTERA CORP Implementation of redundancy on a programmable logic device 
Buy PDF- 142pp WO9410754 1994-05  H03K 19/177 XILINX, INC. IMPROVED CONFIGURABLE CELLULAR ARRAY 
Buy PDF- 81pp WO9522205 1995-08  H03K 19/177 XILINX, INC. TILE BASED ARCHITECTURE FOR FPGA 


Other Abstract Info: DERABS G1996-499784 DERABS G1996-499786 DERABS G1996-499788 DERABS G1999-388168 DERABS G1999-388169 DERABS G1999-388170

Other References:
  • R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2,pp. 203-41, Apr. 1967.
  • S. E. Wahlstrom, "Programmable Logic Arrays -Cheaper by the Millions,"Electronics, Dec. 11, 1967, pp. 90-95.
  • Recent Developments in Switching Theory, A Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422.
  • El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-98.
  • El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-62. (11 pages) Cited by 89 patents
  • "XC5000 Logic Cell Array Family, Technical Data, Advance Information, " Xilinx, Inc., Feb. 1995.
  • The Programmable Gate Array Data Book, 1988, Xilinx, Inc., San Jose, CA (see especially page 2-12.
  • ACT Family Field Programmable Gate Array Databook, Apr. 1992, Actel Corporation, Sunnyvale, Ca, pp. 1-35 through 1-44.
  • The Programmable Logic Data Book, 1994, Xilinx, Inc., San Jose, CA, pp. 2-7, 2-12, and 2-13.


  • Continuity Data:
    Application Number Filed Notes

    >US2001000865227< 2001-05-25  is a continuation of
    US1999000328704  1999-06-09   (granted)
         US6259272 issued 2001-07-10   Programmable logic array integrated circuit architectures

    US1999000328704 1999-06-09  is a division of
    US1997000807561  1997-02-28   (granted)
         US5963049 issued 1999-10-05   Programmable logic array integrated circuit architectures

    US2001000865227 2001-05-25  is a non-provisional of provisional
    US1996000021449P  1996-07-10

    US1997000807561 1997-02-28  is a continuation in part of
    US1995000442795  1995-05-17   (granted)
         US5689195 issued 1997-11-18   Programmable logic array integrated circuit devices


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