 |
 |
|
|
|
|
Title: |
US6366121:
Programmable logic array integrated circuit architectures
[ Derwent Title ]

|
Country: |
US United States of America

|
| |
Inventor: |
Cliff, Richard G.; Milpitas, CA
Heile, Francis B.; Santa Clara, CA
Huang, Joseph; San Jose, CA
Lane, Christopher F.; Campbell, CA
Lee, Fung Fung; Milpitas, CA
McClintock, Cameron; Mountain View, CA
Mendel, David W.; Sunnyvale, CA
Ngo, Ninh D.; San Jose, CA
Pedersen, Bruce B.; San Jose, CA
Reddy, Srinivas T.; Fremont, CA
Sung, Chiakang; Milpitas, CA
Veenstra, Kerry; San Jose, CA
Wang, Bonnie I.; Cupertino, CA

|
Assignee: |
Altera Corporation, San Jose, CA
other patents from ALTERA CORPORATION (21885) (approx. 622)
News, Profiles, Stocks and More about this company

|
Published / Filed: |
2002-04-02
/ 2001-05-25

|
Application Number: |
US2001000865227

|
IPC Code: |
Advanced:
H03K 19/173;
H03K 19/177;
Core:
more...
IPC-7:
G06F 7/38;
H03K 19/177;

|
ECLA Code: |
H03K19/173C2; H03K19/177;

|
U.S. Class: |
326/041;
326/039;

|
Field of Search: |
326/041,38,39

|
Priority Number: |

|
Abstract: |
A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

|
Attorney, Agent or Firm: |
Fish & Neave ;
Jackson, Robert R. ;

|
Primary / Asst. Examiners: |
Tokar, Michael; Chang, David D.

|
INPADOC Legal Status: |
None
Family Legal Status Report

|
 |
 |
|
|
|
|
Parent Case: |
CROSS REFERENCE TO RELATED APPLICATIONS
This is a continuation of U.S. patent application Ser. No. 09/328,704, filed Jun. 9, 1999, which is a division of U.S. patent application Ser. No. 08/807,561, filed Feb. 28, 1997 (now U.S. Pat. No. 5,963,049), which is a continuation-in-part of U.S. patent application Ser. No. 08/442,795, filed May 17, 1995 (now U.S. Pat. No. 5,689,195) and which claims the benefit of U.S. provisional patent application No. 60/021,449, filed Jul. 10, 1996. All of these prior applications are hereby incorporated by reference herein in their entireties.

|
Family: |
Show 56 known family members

|
First Claim:
Show all 16 claims |
The invention claimed is:
1. A programmable logic device comprising:
- a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, each of the regions including a plurality of subregions of programmable logic;
- a plurality of interconnection conductors extending parallel to each of the rows;
- driver circuitry associated with each of the interconnection conductors and adapted to drive an applied signal onto the associated interconnection conductor; and
- selection circuitry associated with each driver circuitry and adapted to select an output signal of any one of at least three of the subregions that are respectively located in three of the columns that are adjacent to one another as the signal applied to the associated driver circuitry.

|
Background / Summary: |
Show background / summary

|
Drawing Descriptions: |
Show drawing descriptions

|
Description: |
Show description

|
 |
 |
|
|
|
|
Foreign References: |

|
Other Abstract Info: |
DERABS G1996-499784
DERABS G1996-499786
DERABS G1996-499788
DERABS G1999-388168
DERABS G1999-388169
DERABS G1999-388170

|
Other References: |
R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2,pp. 203-41, Apr. 1967.
S. E. Wahlstrom, "Programmable Logic Arrays -Cheaper by the Millions,"Electronics, Dec. 11, 1967, pp. 90-95.
Recent Developments in Switching Theory, A Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422.
El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-98.
El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-62.
(11 pages)
Cited by 89 patents
"XC5000 Logic Cell Array Family, Technical Data, Advance Information, " Xilinx, Inc., Feb. 1995.
The Programmable Gate Array Data Book, 1988, Xilinx, Inc., San Jose, CA (see especially page 2-12.
ACT Family Field Programmable Gate Array Databook, Apr. 1992, Actel Corporation, Sunnyvale, Ca, pp. 1-35 through 1-44.
The Programmable Logic Data Book, 1994, Xilinx, Inc., San Jose, CA, pp. 2-7, 2-12, and 2-13.

|
Continuity Data: |
| Application Number | Filed | Notes |
|
|
>US2001000865227< | 2001-05-25 | is a
continuation of |
|
US1999000328704
| 1999-06-09 |
(granted)
|
| |
US6259272 issued 2001-07-10 Programmable logic array integrated circuit architectures
|
|
|
|
US1999000328704 | 1999-06-09 | is a
division of |
|
US1997000807561
| 1997-02-28 |
(granted)
|
| |
US5963049 issued 1999-10-05 Programmable logic array integrated circuit architectures
|
|
|
|
US2001000865227 | 2001-05-25 | is a
non-provisional of provisional |
|
US1996000021449P
| 1996-07-10 |
|
|
|
US1997000807561 | 1997-02-28 | is a
continuation in part of |
|
US1995000442795
| 1995-05-17 |
(granted)
|
| |
US5689195 issued 1997-11-18 Programmable logic array integrated circuit devices
|
|

|


|
Nominate this for the Gallery...

|
|