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 Title: |
US6525607:
High-voltage differential input receiver
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Liu, Jonathan H.; Folsom, CA
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| Assignee: |
Intel Corporation, Santa Clara, CA
other patents from INTEL CORPORATION (278220) (approx. 7,414)
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| Published / Filed: |
2003-02-25
/ 2000-09-27
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| Application Number: |
US2000000669900
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| IPC Code: |
Advanced:
H03F 1/52;
H03F 3/45;
Core:
more...
IPC-7:
H03F 1/52;
H03F 3/45;
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| ECLA Code: |
H03F1/52; H03F3/45S1A1; H03F3/45S3A;
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| U.S. Class: |
330/253;
330/298;
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| Field of Search: |
330/253,258,261,298
327/309
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| Priority Number: |
| 2000-09-27 |
US2000000669900 |
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| Abstract: |
A high-voltage differential input receiver interfaces with an external channel. The differential input receiver includes a first stage, a second stage, and a third stage, which incrementally reduce in stages the common mode of a differential signal received from the external channel. During a power-down mode, clamping circuits in the differential input receiver clamp the voltage at nodes in the differential input receiver, and clamp the differential output from the first stage, to a predetermined voltage to prevent electrical overstress of oxide layers of n-channel and p-channel devices in the differential input receiver. Consequently, electrical overstress of oxide layers is prevented, and the voltage swing level of inputs from the external channel is reduced in stages from a higher voltage level to a lower voltage level.
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| Attorney, Agent or Firm: |
Antonelli, Terry, Stout & Kraus, LLP ;
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| Primary / Asst. Examiners: |
Mottola, Steven J.;
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 36 claims |
What is claimed is:
1. A receiver, comprising:
- a first differential amplifier stage that receives a differential input signal from an external channel and produces a first differential output signal based on the differential input signal;
- a second differential amplifier stage that receives the first differential output signal and produces a second differential output signal based on the first differential output signal; and
- a clamping circuit to clamp the first differential output signal of the first differential amplifier stage to a predetermined voltage level during at least one predetermined mode to prevent electrical overstress (EOS) in gate oxide layers of at least the first differential amplifier stage during the at least one predetermined mode.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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