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 Title: |
EP0208428B1:
Direct input/output in a virtual memory system[German][French]
[ Derwent Title ]
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Country:
Kind: |
EP European Patent Office (EPO)
B1 PATENT SPECIFICATION i
(See also:
EP0208428A2,
EP0208428A3 )
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| Inventor: |
Boettner, Steven C.;
James, David V.;
Bryg, William R.;
Liu, Tso-Kai;
Mahon, Michael J.;
Worley, William S.;
Miller, Terrence C.;
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| Assignee: |
Hewlett-Packard Company
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| Published / Filed: |
1993-10-27
/ 1986-06-12
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| Application Number: |
EP1986000304492
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| IPC Code: |
Advanced:
G06F 12/02;
G06F 12/06;
G06F 12/14;
Core:
more...
IPC-7:
G06F 12/08;
G06F 12/10;
G06F 12/14;
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| Priority Number: |
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| Abstract: |
[From equivalent
EP0208428A2]
A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.
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| Attorney, Agent or Firm: |
Colgan, Stephen James et al ;
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| INPADOC Legal Status: |
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| Designated Country: |
CH DE FR GB IT LI NL SE
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| Family: |
Show 18 known family members
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First Claim:
Show all claims |
1. A computing system comprising a plurality of input/output devices (103-107) which each include a plurality of registers (400-405) for controlling the input/output device, local memory means (102) having a number of physical storage locations smaller than the number of entries in the memory portion (371) of the address space (370), and system processing means (101) for executing a plurality of processes, characterized in that:
the system processing means (101) includes mapping means (701, 550) for assigning first and second pages (302, 301) of addresses to each of the input/output devices (103-107), said first page (302) having a higher privilege level than said second page (301), as defined by respective access right codes (507, 517), said registers (400-405) being either fully implemented in both said first and second pages (302, 301) or fully implemented in said first page (302) and partially implemented in said second page (301), said registers (401, 404, 405) which are fully implemented in both of said first and second pages each being accessible for read/write operations by processes of low privilege and said registers (400, 402, 403) which are fully implemented in said first page (302) and partially implemented in said second page (301) being accessible by processes of low privilege for read only operations, or alternatively being neither accessible for read nor write operations by processes of low privilege.
[German]
[French]
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Description
Expand description |
+ Background
The present invention concerns virtual memory systems in general and as they pertain to the way a computing system processor allows processes to access input/output (I/O) devices. In the prior art, each process running on a computer system has had its own virtual address space. This can lead to very complex systems and non-optimal performance. For instance, a separate page table needs to be kept for each process. A page table maps virtual memory addresses to physical locations in memory. Furthermore, if each process has its own virtual address space, each time processes are swapped in a computer, translation buffers and cache entries from the prior process must be invalidated.
+ Brief Description of the Drawings
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