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 Title: |
EP0231574B1:
Cache-based computer systems[German][French]
[ Derwent Title ]
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Country:
Kind: |
EP European Patent Office (EPO)
B1 PATENT SPECIFICATION i
(See also:
EP0231574A2,
EP0231574A3 )
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| Inventor: |
Moussouris, John P.;
Crudele, Lester M.;
Przybylski, Steven A.;
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| Assignee: |
MIPS COMPUTER SYSTEMS, INC.
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| Published / Filed: |
1992-12-16
/ 1986-07-11
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| Application Number: |
EP1986000305356
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| IPC Code: |
Advanced:
G06F 12/08;
G06F 12/10;
Core:
more...
IPC-7:
G06F 12/08;
G06F 12/10;
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| Priority Number: |
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| Abstract: |
[From equivalent
EP0231574A2]
A cache-based computer architecture in which an address generating unit (12) and a tag comparator (14) are packaged together and separately from cache RAMs (26,28). If the architecture supports virtual memory, an address translation unit (50) may be included on the same chip (10) as, and logically between, the address generating unit and the tag comparator (14) logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses (22,16,24).
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| Attorney, Agent or Firm: |
Pilch, Adam John Michael et al ;
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| INPADOC Legal Status: |
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| Designated Country: |
AT BE CH DE FR GB IT LI LU NL SE
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| Family: |
Show 20 known family members
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First Claim:
Show all claims |
1. A computer system comprising:
a package (10) containing an address generating unit (12) and a tag comparator (14);
a first set (26,28) of cache memory comprising a first cache data memory (28) and a first cache tag memory (26);
data bus means (16) in communication with the first cache data memory (28) and for coupling to a main memory control unit (30);
tag bus means (24) in communication with the tag comparator (14) and the first cache tag memory (26) and for coupling to the main memory control unit (30);
address bus means comprising a first group (54) of m address leads and a second group (22) of n address leads, the first group (54) of address leads being in communication with the tag comparator (14) and the second group (22) of address leads being in communication with the first cache tag memory (26) and the first cache data memory (28) and for coupling to the main memory control unit (30); and
first connection means (18 ) for placing the first group (54) of address leads and the second group (22) of address leads in communication with the address generating unit (12);
characterised in that the first set of cache memory (26,28) is disposed externally to the package (10).
[German]
[French]
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Description
Expand description |
This invention relates to cache-based computer systems, and more particularly but not exclusively to such computer systems which employ cache RAMs (random access memories).
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