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 Title: |
EP0328450B1:
Direct memory access controller[German][French]
[ Derwent Title ]
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Country:
Kind: |
EP European Patent Office (EPO)
B1 PATENT SPECIFICATION i
(See also:
EP0328450A2,
EP0328450A3 )
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| Inventor: |
Taniai, Takayoshi;
Tanaka, Yasuhiro;
Saitoh, Tadashi;
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| Assignee: |
FUJITSU LIMITED
FUJITSU DEVICES INC
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| Published / Filed: |
1996-08-28
/ 1989-02-07
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| Application Number: |
EP1989000400344
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| IPC Code: |
Advanced:
G06F 9/22;
G06F 9/315;
G06F 13/28;
Core:
G06F 13/20;
more...
IPC-7:
G06F 13/28;
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| ECLA Code: |
G06F9/22D; G06F9/22F; G06F9/315; G06F13/28;
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| Priority Number: |
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| Abstract: |
[From equivalent
EP0328450A2]
A direct memory access controller coupled to a system bus (38, 39) for controlling a data transfer by a direct memory access comprises an internal bus (37), a data handler (36) coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer (21) which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part (22) supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles. Each data transfer between the input/output device and the memory device is controlled by the microprograms of the microsequencer in cooperation with the programmable logic array part.
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| Attorney, Agent or Firm: |
Joly, Jean-Jacques et al ;
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| INPADOC Legal Status: |
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| Designated Country: |
DE FR GB
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| Family: |
Show 10 known family members
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First Claim:
Show all claims |
1. A direct memory access controller coupled to a system bus (38, 39) of a system including an input/output device (51) and a memory device (52), for controlling a data transfer by direct memory access, said direct memory access controller comprising :
- an internal bus (37);
- a data handler (36) coupled to said system bus (38, 39) and said internal bus (37) for controlling an exchange of data between said system bus (38, 39) and said internal bus (37);
- a microsequencer (21) which controls by microprograms the system state during each of a plurality of system clock cycles comprised in a present transfer cycle, that is the microsequencer (21) controls the operating states of parts of the direct memory access controller in units of one system clock cycle during a present transfer cycle; and
- a programmable logic array part (22), a data transfer between the input/output device (51) and the memory device (52) being controlled by the microprograms of the microsequencer (21) in co-operation with said programmable logic part (22);
- said direct memory access controller being characterized in that the programmable logic array part (22) is arranged to be supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count and is coupled to the internal bus (37) for outputting control information required during the next transfer cycle, and wherein the microsequencer (21) is adapted to control the sequence of system states passed through in the successive system clock cycles of the present transfer cycle whereas the programmable logic array part (22) is adapted to control the sequence of transfer cycles put into effect by the direct memory access controller.
[German]
[French]
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Description
Expand description |
+ BACKGROUND OF THE INVENTION
The present invention generally relates to direct memory access controllers, and more particularly to a direct memory access controller for controlling a direct memory access in which data is transferred directly between a memory device and an input/output device at a high speed during a time when a central processing unit forfeits exclusive right to a system bus of a data processing apparatus having the central processing unit.
+ SUMMARY OF THE INVENTION
+ Brief Description of the Drawings
+ DETAILED DESCRIPTION
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| Other Abstract Info: |
DERABS G89-235765
JAPABS 130502P000077
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