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Title: JP61180476A2: SEMICONDUCTOR DEVICE
[ Derwent Title ]


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Kind:
JP Japan
A

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Inventor: ENDO SHIGENARI;

Assignee: NEC CORP
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Published / Filed: 1986-08-13 / 1985-02-05

Application Number: JP1985000020436

IPC Code: Advanced: H01L 29/47; H01L 29/872;
Core: H01L 29/40; H01L 29/66;
IPC-7: H01L 29/48;
H01L 29/91;

ECLA Code: H01L29/47;

Priority Number:
1985-02-05  JP1985000020436

Abstract:     PURPOSE: To prevent intrusion of metal into a ground semiconductor layer and to improve thermal resistance by a method wherein the first metallic layer contacting with the ground semiconductor layer is provided and thereon in addition the second metallic layer and the third metallic layer made of transition metallic nitride are provided.
    CONSTITUTION: An Si semiconductor epitaxial layer 12 is grown on high impurity density N+-type Si semiconductor substrate 11. An oxidate guard film 13 is provided on the epitaxial layer 12 by using thermal oxidization measure, and an aperture section for an electrode is provided to the oxidate guard film 13 by using chemical etching measure. Schottky barrier metallic layer 14 is provided to the aperture section and additionally a nitride layer 15 such, as Ti etc. is provided. An Al layer 16 is provided on the nitride layer 15 for using as an outgoing electrode.
    COPYRIGHT: (C)1986,JPO&Japio

Family: None

Other Abstract Info: DERABS G86-254212 DERG86-254212

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