 |
 |
|
|
|
|
Title: |
US3701143:
WALSH FUNCTION GENERATOR

|
Country: |
US United States of America

|
| |
Inventor: |
Nacht, George G.; Oxon Hill, MD

|
Assignee: |
The United States of America as represented by the Secretary of the Navy
other patents from UNITED STATES OF AMERICA, NAVY (597270) (approx. 13,239)
News, Profiles, Stocks and More about this company

|
Published / Filed: |
1972-10-24
/ 1970-08-24

|
Application Number: |
US1970000066418

|
IPC Code: |
Advanced:
H04L 25/49;
Core:
more...
IPC-7:
H04L 3/00;

|
U.S. Class: |
Current:
341/050;
370/209;
708/410;
Original:
340/347.DD;
179/015.OR;
179/015.BC;

|
Field of Search: |
340/347
179/15 OR,15 BC

|
Priority Number: |
| 1970-08-24 |
US1970000066418 |

|
Abstract: |
A clock driven generator which produces desired Walsh functions in response to binary number input command signals. The input command signals are connected to be operated on by various circuitry and thereby produce output signals which are individually a particular bit of a desired Walsh function. The Walsh function is obtained by scanning the output signals.

|
Attorney, Agent or Firm: |
Sciascia, R. S. ;
Branning, Arthur L. ;
Murray, James G. ;

|
Primary / Asst. Examiners: |
Robinson, Thomas A.; Glassman, Jeremiah

|
INPADOC Legal Status: |
None
Family Legal Status Report

|
Family: |
Show 2 known family members

|
First Claim:
Show all 2 claims |
What is claimed and desired to be secured by Letters Patent of the United
1. A Walsh function generator comprising:
- combining circuit means including a plurality of Material Equivalence circuits for receiving N input command signals of binary type and for producing 2N output signals according to predetermined logic; and
- scanning means having a single output terminus to sequentially sample said 2N output signals,
- said sequential signals forming the Walsh function associated with the particular input-signal combination being received by said combining circuit means,
- one of said output signals being a constant value, N other of said output signals being the inverse of said N input signals, and the remaining 2N -(N+1) of said 2N output signals being obtained from circuits

|
Background / Summary: |
Show background / summary

|
Drawing Descriptions: |
Show drawing descriptions

|
Description: |
Show description

|
Forward References: |
Show 7 U.S. patent(s) that reference this one

|