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Title: |
US3795864:
METHODS AND APPARATUS FOR GENERATING WALSH FUNCTIONS
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Fullton, Jr., James McFerrin; Chapel Hill, NC

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Assignee: |
Western Electric Company, Incorporated, New York, NY
other patents from AT&T CORP. (706518) (approx. 16,328)
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Published / Filed: |
1974-03-05
/ 1972-12-21

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Application Number: |
US1972000317340

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IPC Code: |
Advanced:
H04J 11/00;
H04L 23/02;
Core:
H04L 23/00;
more...
IPC-7:
H04J 3/00;

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U.S. Class: |
Current:
708/410;
341/178;
370/209;
375/242;
375/259;
708/270;
708/273;
Original:
325/038.R;
178/068;
235/197;
179/015.BC;
340/348;

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Field of Search: |
179/15 BC
235/154,197
325/38 R
340/348
178/068

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Priority Number: |
| 1972-12-21 |
US1972000317340 |

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Abstract: |
Apparatus for generating digital signals which are representative of the Walsh functions. In a first embodiment, a selection register receives the row address of a given row in a Hadamard array which corresponds to the desired Walsh functions. A binary counter receives the column address at which generation of the Walsh function is to begin and the outputs of the register and counter are selectively "AND"ed and "OR"ed, according to a predetermined procedure, to generate the desired Walsh function.

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Attorney, Agent or Firm: |
Sheffield, B. W. ;

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Primary / Asst. Examiners: |
Griffin, Robert L.; Bookbinder, Marc E.

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INPADOC Legal Status: |
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Family: |
None

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First Claim:
Show all 21 claims |
1. A method of generating a digital signal which is representative of the Kth Walsh function of order n, where n = 2p, p >=1, and 0 <=K<=n-1, comprising the steps of:
- "anding" each bit in the binary address of the K row of an n × n Hadamard array of the Walsh functions of order n, with the corresponding bit in the binary address of the mth column in said array, where 0<=m<=n-1;
- generating a first signal if the number of "1"s in the binary word resulting from said "anding" step is even, and a second signal if otherwise; and then
- reiterating said "anding" and said generating steps, seriatim, for the m+1th, m+2th, . . . n-1th, 0th, . . . m-1th column of the array, the sequence of first and second signals so produced

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Background / Summary: |
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Drawing Descriptions: |
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Description: |
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Forward References: |
Show 32 U.S. patent(s) that reference this one

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