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Title: US4410940: Transfer of control method and means among hierarchical cooperating sequential processes
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Country: US United States of America

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11 pages

 
Inventor: Carlson, Eric D.; Los Gatos, CA
Gladney, Henry M.; Saratoga, CA
Lucas, Peter; San Jose, CA
Weller, Daniel L.; San Jose, CA
Zilles, Stephen N.; Los Gatos, CA

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 1983-10-18 / 1980-12-05

Application Number: US1980000213268

IPC Code: Advanced: G06F 9/48;
Core: G06F 9/46;
IPC-7: G06F 9/06;

ECLA Code: G06F9/48C4S;

U.S. Class: Current: 718/106;
Original: 364/200; 364/300;

Field of Search: 364/200 MS File,900 MS File,300

Priority Number:
1980-12-05  US1980000213268

Abstract:     A method for transferring control between hierarchically related cooperating sequential processes P and Q executable in a multi-processing CPU environment. The method uses pointers to identify active and suspended processes. The method steps comprise generating and memory storing activation records; transferring control from process P to process Q, and updating the process pointers to record the suspension of process P and the activation of process Q; and resuming execution in the most recently executing subprocesses of Q by reference to the process pointers. There is stored in memory one activation record per process. The record includes a pointer to the activation that is the parent of the process, a pointer to the most recently executing subprocess of the process, and information defining the current execution state of the process. These pointers are further constrained such that the set of activation records form the nodes of a tree whose arcs are defined by the parent pointers. The descendants of any node P, together with P itself, constitute the subprocesses of P. For any node P the process pointer of P always points to a subprocess of P. The transfer of control from process P to process Q involves the concurrent updating of the process pointers to record the suspension of process P and the activation of process Q.

Attorney, Agent or Firm: Brodie, R. Bruce ;

Primary / Asst. Examiners: Nusbaum, Mark E.; Harkcom, Gary V.

Family: None

First Claim:
Show all 3 claims
We claim:     1. A digital computer implemented method for maintaining synchronous computations among a set of recursively nested cooperating sequential processes, comprising the steps of:
  • (a) generating and storing in memory an activation record (AR) for each process, each AR including a pointer (PARENT) to the AR of the immediate antecedent process, the set of PARENT pointers defining a tree graph ordering or nesting structure, each subtree of which is itself such a structure with a root process and descendent processes, each AR further including a pointer (PROCESS) to the AR of the most recently activated process within the least inclusive subtree ordering of which it is a member, and information defining the current execution state of the process; and
  • (b) responsive to execution of an instruction, transferring control to a process within the set of processes:
    • (i) ascertaining the nearest antecedent of both the transferring and the transferred to processes using the PARENT pointers;
    • (ii) updating the PROCESS pointers of all the processes between the closest antecedent process and the transferred to process so that they designate the antecedents in sequence to the transferred to process;
    • (iii) following the PROCESS pointers from the transferred to process to the most recently executing process in the subtree it roots, and resuming the execution of the transferred to process.


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Forward References: Show 23 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (23)   |   Backward references (8)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
  US3614740  1971-10 Delagi et al.  Digital Equipment Corporation DATA PROCESSING SYSTEM WITH CIRCUITS FOR TRANSFERRING BETWEEN OPERATING ROUTINES, INTERRUPTION ROUTINES AND SUBROUTINES
Buy PDF- 42pp US4016545  1977-04 Lipovski  Harris Corporation Plural memory controller apparatus
Buy PDF- 48pp US4084224  1978-04 Appell et al.  Compagnie Honeywell Bull System of controlling procedure execution using process control blocks
Buy PDF- 14pp US4149240  1979-04 Misunas et al.  Massachusetts Institute of Technology Data processing apparatus for highly parallel execution of data structure operations
Buy PDF- 9pp US4152761  1979-05 Louie  Intel Corporation Multi-task digital processor employing a priority
Buy PDF- 9pp US4173782  1979-11 Dixon  International Business Machines Corporation Return and link mechanism
Buy PDF- 69pp US4297743  1981-10 Appell et al.  Compagnie Honeywell Bull Call and stack mechanism for procedures executing in different rings
Buy PDF- 16pp US4330822  1982-05 Dodson  Burroughs Corporation Recursive system and method for binding compiled routines
       
Foreign References:
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Publication Date IPC Code Assignee   Title
Buy PDF GB1240978 1971-07  G06F 9/46 IBM DATA PROCESSING SYSTEMS 


Other References:
  • W. A. Wulf et al., Fundamental Structures of Computer Science, Addison Wesley Pub. Co., Chapter 14, pp. 375-396 (1981).
  • E. I. Organick, Computer System Organization, Academic Press (1973), pp. 49-55.
  • Wang, Arne and Dahl, Ole-Johan, "Coroutine Sequencing in a Block Structured Environment", BIT, vol. 11, 1971, pp. 425-449.
  • Hanson, David R., "The SL5 Procedure Mechanism", Communications of the ACM, vol. 21, No. 5, May 1978, pp. 392-400. (9 pages)
  • Bobrow, Daniel G. and Wegbreit, "A Model and Stack Implementation of Multiple Environments", CACM, vol. 16, No. 10, Oct. 1973.


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