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Title: US4802122: Fast flush for a first-in first-out memory
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Country: US United States of America

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Inventor: Auvinen, Stuart T.; Capitola, CA
Hoberman, Barry A.; Mountain View, CA

Assignee: Advanced Micro Devices, Inc., Sunnyvale, CA
other patents from ADVANCED MICRO DEVICES, INC. (8075) (approx. 6,737)
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Published / Filed: 1989-01-31 / 1987-04-28

Application Number: US1987000043521

IPC Code: Advanced: G06F 5/10; G11C 8/16; G11C 11/41;
Core: G06F 5/06; G11C 8/00; more...
IPC-7: G11C 11/00;

ECLA Code: G06F5/10; G11C8/16;

U.S. Class: Current: 365/154; 365/190; 365/218; 365/221;
Original: 365/154; 365/190;

Field of Search: 365/154,156,189,190,202

Priority Number:
1987-04-28  US1987000043521

Abstract: In a memory circuit including a write bit-line for writing data into a memory cell, and a read bit-line for reading data from the cell, a transistor is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.

Attorney, Agent or Firm: MacPherson, Alan H. ; Winters, Paul J. ; Ogonowsky, Brian D. ;

Primary / Asst. Examiners: Popek, Joseph A.;

Maintenance Status: B1 Re-examined

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Related Applications: Go to Result Set: 1 patent(s) that list this one as related
Application Number Filed Patent Pub. Date  Title
     1989-01-31  Fast flush for a first-in first-out memory


       
Designated Country: DE FR GB NL 

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First Claim:
Show all 4 claims
We claim:     1. A circuit for reducing the fall-through delay of data in a memory cell comprising:
  • a write bit-line connected with the memory cell for communicating data to the cell;
  • a read bit-line connected with the memory cell for communicating data from the cell; and
  • means selectively connecting the write bit-line with the read bit-line independent of the memory cell so that data carried by the write bit-line can be communicated to the read bit-line independent of the memory cell.


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Forward References: Show 30 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (30)   |   Backward references (3)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 8pp US4447891  1984-05 Kadota  Matsushita Electric Industrial Co., Ltd. Simultaneous read-write IGFET memory cell
Buy PDF- 8pp US4535427  1985-08 Jiang  Mostek Corporation Control of serial memory
Buy PDF- 12pp US4541076  1985-09 Bowers et al.  Storage Technology Corporation Dual port CMOS random access memory
       
Foreign References: None

Other Abstract Info: DERABS G88-308874

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