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 Title: |
US4807115:
Instruction issuing mechanism for processors with multiple functional units
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Torng, Hwa C.; Ithaca, NY
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| Assignee: |
Cornell Research Foundation, Inc., Ithica, NY
other patents from CORNELL RESEARCH FOUNDATION INC. (123370) (approx. 895)
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| Published / Filed: |
1989-02-21
/ 1987-10-14
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| Application Number: |
US1987000112020
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| IPC Code: |
Advanced:
G06F 9/38;
G06F 15/78;
Core:
G06F 15/76;
more...
IPC-7:
G06F 13/00;
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| U.S. Class: |
Current:
712/215;
712/217;
712/E09.049;
Original:
364/200;
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| Field of Search: |
364/200 MS File,900 MS File
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| Priority Number: |
| 1983-10-07 |
US1983000539854 |
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| Abstract: |
An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.
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| Attorney, Agent or Firm: |
Sughrue, Mion, Zinn, Macpeak & Seas ;
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| Primary / Asst. Examiners: |
Zache, Raulfe B.; Munteanu, Florin
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| INPADOC Legal Status: |
Show legal status actions
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| Foreign References: |
None
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| Other References: |
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, Jan. 1967.
R. M. Keller, "Look-Ahead Processors", Computing Surveys, vol. 7, No. 4, Dec. 1975.
J. W. Bowra and H. C. Torng, "The Modeling and Design of Multiple Function-Unit Processors", IEEE Transactions on Computers, vol. C-25, No. 3, Mar. 1976.
Siewiorek, D. P. "Computer Structures: Principles and Examples", 1982, pp. 278, 288-292.
H. C. Torng et al., "An Instruction Issuing Approach to Enchancing Performance in Multiple Functional Units Processors", IEEE Transactions on Computers, vol. C-35, No. 9, Sep. 86.
J. E. Thornton, "Parallel Operation in the Control Data", A FIES Proceedings, vol. 26, pt. 2, 1964, pp. 489-496.
G. Bell et al., "The Cray-1 Computer System", Comm. of the ACM, vol. 21, No. 1, Jan. 1978.
V. P. Srinii and J. F. Asenjo, "Analysis of Cray-1S Architecture", ACM, 1983.
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