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Title: US4868522: Clock signal distribution device
[ Derwent Title ]


Country: US United States of America

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17 pages

 
Inventor: Popat, Kaushik; Pleasanton, CA
MacMillan, David; Sunnyvale, CA

Assignee: Gazelle Microcircuits, Inc., Santa Clara, CA
other patents from GAZELLE MICROCIRCUITS, INC. (215790) (approx. 29)
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Published / Filed: 1989-09-19 / 1988-12-13

Application Number: US1988000283686

IPC Code: Advanced: G06F 1/10; H03L 7/07; H03L 7/081;
Core: more...
IPC-7: H03B 27/00; H03L 7/06;

U.S. Class: Current: 331/002; 327/231; 331/055;
Original: 331/002; 331/055;

Field of Search: 331/002,55,56,172 375/109 455/051,69

Priority Number:
1988-12-13  US1988000283686

Abstract: A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.

Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel ;

Primary / Asst. Examiners: Mis, David;

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 19 claims
We claim:     1. A signal distribution device for applying a transmit signal simultaneously to a plurality of receiving devices comprising:
  • a plurality of first adjustable delay elements each having an input signal to be applied to said receiving devices and each having an output for coupling a transmit signal to an associated one of said receiving devices;
  • a plurality of second adjustable delay elements identical to said plurality of first delay elements, each of said second delay elements being associated with one of said first delay elements, each of said second delay elements having an input for receiving a return signal returning from each of said receiving devices and each having an output; and
  • a plurality of detecting means each coupled to an output of an associated second delay element for detecting relative propagation delays, a particular propagation delay being associated with each receiving device, of said transmit signal as said transmit signal is communicated from said signal distribution device to each of said receiving devices and back to said signal distribution device as said return signal and for providing a plurality of control signals for application to said first and second delay elements, wherein each of said control signals identically controls an associated pair of first and second delay elements to delay said transmit signal an amount necessary for said transmit signal to arrive at all of said receiving devices simultaneously.


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Forward References: Show 58 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (58)   |   Backward references (3)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 21pp US4411007  1983-10 Rodman et al.  The Manitoba Telephone System Distributed network synchronization system
Buy PDF- 20pp US4497056  1985-01 Sugamori  Takeda Riken Co. Ltd. IC Tester
Buy PDF- 15pp US4577318  1986-03 Whitacre et al.  Burroughs Corporation Self testing detection system for comparing digital signal transition times
       
Foreign References:
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Publication Date IPC Code Assignee   Title
  JP55070757 1980-05       


Other References:
  • M. Johnson et al., "A Variable Delay Line Phase Locked Loop for CPU-Coprocessor Synchronization", IEEE Int. Solid-State Circuits Conference, 1988, pp. 142, 143.


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