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Title: US4933940: Operations controller for a fault tolerant multiple node processing system
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Country: US United States of America

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107 pages

 
Inventor: Walter, Chris J.; Columbia, MD
Kiekhafer, Roger M.; Lincoln, NE
Finn, Alan M.; Amston, CT

Assignee: Allied-Signal Inc., Morris Township, Morris County, NJ
other patents from ALLIED-SIGNAL INC. (19715) (approx. 6,414)
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Published / Filed: 1990-06-12 / 1989-05-12

Application Number: US1989000351876

IPC Code: Advanced: G06F 9/46; G06F 9/50; G06F 11/00; G06F 11/18; G06F 11/20; G06F 15/16; G06F 11/10;
Core: more...
IPC-7: G06F 11/00;

ECLA Code: G06F11/18V4; G06F9/48C4S; G06F11/00C3; G06F11/18E; G06F11/18M; G06F11/18V; G06F15/16D; S06F11/00B2; S06F11/10; S06F11/18; S06F11/18E; S06F11/18M;

U.S. Class: Current: 714/010; 714/015; 714/E11.016;
Original: 371/009.1; 371/011.3; 371/016.5;

Field of Search: 371/009,11,16,29,9.1,11.3,16.1,29.1,16.5

Priority Number:
1989-05-12  US1989000351876
1987-04-15  US1987000038813
1987-04-15  US1987000038818
1987-04-15  US1987000039190

Abstract:     A fault tolerator for an operations controller of a multiple node fault tolerant processing system having a data memory for storing the content of all received error free messages, an error file for storing the content of all received inner node error reports, an error handler for generating a base penalty count for each node based on the content of the errors recorded in the error file and for excluding each node from the operation of the multiple node processing system whose base penalty count exceeds an exclusion threshold. The fault tolerator also includes a synchronizer interface for passing the selected fields of the received messages to a synchronizer, a scheduler interface for passing selected information to a scheduler, and a message interface which stores the error free messages in the data memory and passes the selected fields of the messages to the synchronizer.

Attorney, Agent or Firm: Massung, Howard G. ; Walsh, Robert A. ;

Primary / Asst. Examiners: Atkinson, Charles E.;

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

       
Related Applications:
Application Number Filed Patent Pub. Date  Title
US1987000038813 1987-04-15       


       
Parent Case:     This is a division of application Ser. No. 038,813 filed Apr. 15, 1987.

Designated Country: DE FR GB IT  EP JP 

Family: Show 11 known family members

First Claim:
Show all 18 claims
What is claimed is:     1. In a multiple node fault tolerant processing system having a plurality of nodes wherein each node has an applications processor for executing a predetermined set of tasks and an operations controller for controlling its own node in coordination with all of the other nodes of said plurality of nodes through the exchange of inter-node messages and wherein said operations controller selects the tasks to be executed by the applications processor from said predetermined set of tasks, each operations controller having a plurality of subsystems including a message checker, a scheduler, a synchronizer and a voter, each of which is capable of detecting errors and generating internal error reports identifying each error detected, each operations controller further having at least two operating system states and operative to switch from one operating system state to another in response to the exclusion of a faulty node or the readmittance of a healthy node which changes the number of nodes operating in the processing system, a fault tolerator for said operations controller comprising:
  • a message memory storing the content of all inter-node messages received by said operations controller;
  • an error file storing the content of said internal error reports generated by said message checker, said scheduler, said synchronizer and said voter;
  • error handler means for storing said error reports in said error file and for generating a base penalty count for each node of said plurality of nodes from the content of said error file, said base penalty count being indicative of the operational status of the associated node, said error handler means further having means for determining which nodes are faulty and for excluding such faulty nodes from participating in the operation of said multiple node processing system, in coordination with all of the other nodes in the system, through the exchange of inter-node messages, said inter-node messages including error messages containing the content of said error file for a particular node and a base penalty count message containing said base penalty count of each node; and
  • interface means for storing all of the messages passed by the message checker in said message memory, for passing the identities of the faulty nodes to the scheduler and the synchronizer, and for passing all error reports to said error handler.


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Forward References: Show 55 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (55)   |   Backward references (5)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 4pp US4392199  1983-07 Schmitter et al.  Siemens Aktiengesellschaft Fault-tolerant system employing multi-microcomputers using two-out-of-three majority decision
Buy PDF- 28pp US4438494  1984-03 Budde et al.  Intel Corporation Apparatus of fault-handling in a multiprocessing system
Buy PDF- 16pp US4503534  1985-03 Budde et al.  Intel Corporation Apparatus for redundant operation of modules in a multiprocessing system
Buy PDF- 24pp US4503535  1985-03 Budde et al.  Intel Corporation Apparatus for recovery from failures in a multiprocessing system
Buy PDF- 15pp US4554661  1985-11 Bannister  Burroughs Corporation Generalized fault reporting system
       
Foreign References: None

Other Abstract Info: DERABS G88-307662

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