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 Title: |
US4954987:
Interleaved sensing system for FIFO and burst-mode memories
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Auvinen, Stuart T.; Santa Cruz, CA
Hoberman, Barry A.; Mountain View, CA
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| Assignee: |
Advanced Micro Devices, Inc., Sunnyvale, CA
other patents from ADVANCED MICRO DEVICES, INC. (8075) (approx. 6,737)
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| Published / Filed: |
1990-09-04
/ 1989-07-17
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| Application Number: |
US1989000380368
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| IPC Code: |
Advanced:
G11C 7/10;
G11C 11/401;
G11C 11/409;
G11C 11/419;
G06F 5/00;
Core:
more...
IPC-7:
G11C 13/00;
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| U.S. Class: |
Current:
365/189.02;
365/189.05;
365/203;
365/230.02;
365/230.04;
365/230.08;
Original:
365/189.02;
365/189.05;
365/230.02;
365/230.08;
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| Field of Search: |
365/189.01,189.02,230.04,189.05,189.09,230.02,233,230.08
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| Priority Number: |
| 1989-07-17 |
US1989000380368 |
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| Abstract: |
An interleaved sensing system for decreasing the read access time in a sequential memory includes a sequential memory array formed of a plurality of memory cells for storing data. The memory cells are arranged in a plurality of odd columns and a plurality of even columns. Sensing means are provided for interleaving the stored data in the memory cells in the odd columns with the stored data in the memory cells in the even columns. An output buffer is coupled to the sensing means for generating data output representing alternately the stored data in the odd and even columns during alternate read cycles.
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| Attorney, Agent or Firm: |
Chin, Davis ;
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| Primary / Asst. Examiners: |
Fears, Terrell W.;
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| Maintenance Status: |
E1 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
Show 4 known family members
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First Claim:
Show all 20 claims |
What is claimed is:
1. An interleaved sensing system for decreasing the read access time in a sequential memory, comprising in combination:
- a sequential memory array formed of a plurality of memory cells for storing data, said memory cells being arranged in a plurality of odd columns and a plurality of even columns;
- odd bit line means coupled to said plurality of odd columns;
- even bit line means coupled to said plurality of even columns;
- odd selecting means responsive to odd column select signals and coupled to said odd bit line means for accessing and transferring the stored data in selected ones of said memory cells in said odd columns to a pair of odd data lines;
- even selecting means responsive to even column select signals and coupled to said even bit line means for accessing and transferring the stored data in selected ones of said memory cells in said even columns to a pair of odd data lines;
- odd precharging means responsive to an odd precharging signal for precharging said pair of odd data lines prior to the transferring of the stored data in said odd columns to said pair of odd data lines;
- even precharging means responsive to an even precharging signal for precharging said pair of even data lines prior to the transferring of the stored data in said even columns to said pair of even data lines;
- odd sensing means coupled to said pair of odd data lines for sensing said stored data in said odd columns and for generating an odd output signal in response to an odd read signal;
- even sensing means coupled to said pair of even data lines for sensing said stored data in said even columns and for generating an even output signal in response to an even read signal;
- multiplexing means coupled to said odd and even sensing means for alternately supplying said odd output signal and said even output signal in a predetermined timing relationship; and
- output means coupled to said multiplexing means for generating output data representing alternately said stored data in said odd and even columns in response to a read transfer signal.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 64 U.S. patent(s) that reference this one
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