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 Title: |
US4972415:
Voter subsystem for a fault tolerant multiple node processing system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Walter, Chris J.; Columbia, MD
Kieckhafer, Roger M.; Lincoln, NE
Finn, Alan M.; Amston, CT
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| Assignee: |
Allied-Signal Inc., Morris Township, Morris County, NJ
other patents from ALLIED-SIGNAL INC. (19715) (approx. 6,414)
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| Published / Filed: |
1990-11-20
/ 1989-06-07
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| Application Number: |
US1989000362960
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| IPC Code: |
Advanced:
G06F 9/46;
G06F 9/50;
G06F 11/00;
G06F 11/18;
G06F 11/20;
G06F 15/16;
G06F 11/10;
Core:
more...
IPC-7:
G06F 11/08;
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| ECLA Code: |
G06F11/18V4; G06F9/48C4S; G06F11/00C3; G06F11/18E; G06F11/18M; G06F11/18V; G06F15/16D; S06F11/00B2; S06F11/10; S06F11/18; S06F11/18E; S06F11/18M;
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| U.S. Class: |
Current:
714/797;
708/445;
714/E11.016;
Original:
371/036;
364/734;
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| Field of Search: |
364/734
371/036
340/146.1
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| Priority Number: |
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| Abstract: |
A voter subsystem for a multiple node fault tolerant system having an upper medial value sorter for sorting a plurality of received values to generate an upper medial value and a lower medial value sorter for sorting the same plurality of received values to generate a lower medial value. An averaging circuit adds the upper and lower medial values then divides by two to generate a voted value. A deviance checker checks each of the plurality of received values against the voted value to generate a deviance error for each received value which differed from the voted value by a predetermied amount. A loader loads the plurality of received values into the upper and lower medial value sorters and the deviance checker bit-by-bit, starting from the most significant bit positions through the least significant bit positions. The upper and lower medial value sorters and deviance checker process the received values on-the-fly in the order they are received.
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| Attorney, Agent or Firm: |
Massung, Howard G. ;
Walsh, Robert A. ;
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| Primary / Asst. Examiners: |
Atkinson, Charles E.;
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| Maintenance Status: |
CC Certificate of Correction issued
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| INPADOC Legal Status: |
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| Parent Case: |
This is a division of application Ser. No. 038,813, filed Apr. 15, 1987, now U.S. Pat. No. 4,914,657 issued Apr. 3, 1990.
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| Designated Country: |
DE FR GB IT EP JP
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| Family: |
Show 11 known family members
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First Claim:
Show all 38 claims |
What is claimed is:
1. A voter subsystem for a multiple node fault tolerant processing system having a plurality of nodes wherein each node in the multiple node processing system has an applications processor for executing a predetermined set of application tasks and an operations controller for controlling the operation of its own node in coordination with all of the other nodes in the processing system through the exchange of inter-node messages containing data values and operational information and for selecting the application tasks to be executed by the applications processor and wherein each applications task of said predetermined set of application tasks is executed by more than one node, said voter subsystem comprising:
- voter means for processing in parallel the data values contained in said inter-node messages which resulted from the execution of the same task by more than one node to generate a voted data value for that task;
- deviance checker means for comparing in parallel the data values received in each of said inter-node messages with said voted data value to generate a deviance vector identifying each data value contained in said inter-node messages which differed from said voted data value by more than a predetermined deviance value; and
- loader means for loading said data values received in said inter-node messages which resulted from the execution of the same application task into said voter means and said deviance checker means.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 15 U.S. patent(s) that reference this one
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